Patent classifications
H01L29/7725
LACING SYSTEM WITH GUIDE ELEMENTS
An article of footwear with various types of guide elements is disclosed. The article of footwear provides a set of tensile elements that can be moved through the guide elements to switch between a loosened and tightened position of the upper. The tensile elements may be routed through a guide element associated with the upper that can provide compressive strength and support.
SEMICONDUCTOR FIELD-EFFECT TRANSISTOR, POWER AMPLIFIER COMPRISING THE SAME AND MANUFACTURING METHOD THEREOF
A semiconductor field-effect transistor, a power amplifier comprising the same and a manufacturing method thereof are provided herein. The semiconductor field-effect transistor contains an n-type doped layer arranged close to the edge of the two-dimensional electron gas area in a channel layer; said n-type doped layer is arranged to adjust the distribution of electron concentration in the transistor, and to improve the RF linearity of the overall component; thereby not only the threshold voltage can be controlled through the adjustment of the charge, but the contact and series resistance can also be reduced.
LACING SYSTEM WITH GUIDE ELEMENTS
An article of footwear with various types of guide elements is disclosed. The article of footwear provides a set of tensile elements that can be moved through the guide elements to switch between a loosened and tightened position of the upper. The tensile elements may be routed through a guide element associated with the upper that can provide compressive strength and support.
Lacing system with guide elements
An article of footwear with various types of guide elements is disclosed. The article of footwear provides a set of tensile elements that can be moved through the guide elements to switch between a loosened and tightened position of the upper. The tensile elements may be routed through a guide element associated with the upper that can provide compressive strength and support.
Quantum doping method and use in fabrication of nanoscale electronic devices
A novel doping technology for semiconductor wafers has been developed, referred to as a quantum doping process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a quantized set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.
Diamond based current aperture vertical transistor and methods of making and using the same
A semiconductor structure, device, or vertical field effect transistor is comprised of a drain, a drift layer disposed in a first direction relative to the drain and in electronic communication with the drain, a barrier layer disposed in the first direction relative to the drift layer and in electronic communication with the drain, the barrier layer comprising a current blocking layer and an aperture region, a two-dimensional hole gas-containing layer disposed in the first direction relative to the barrier layer, a gate electrode oriented to alter an energy level of the aperture region when a gate voltage is applied to the gate electrode, and a source in ohmic contact with the two-dimensional hole gas-containing layer. At least one of an additional layer, the drain, the drift region, the current blocking layer, the two-dimensional hole gas-containing layer, and the aperture region comprises diamond.
Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ)
According to one embodiment, an apparatus includes a bottom electrode layer positioned above a substrate in a film thickness direction, a source layer positioned above the bottom electrode layer in the film thickness direction, an impact ionization channel (i-channel) layer positioned above the source layer in the film thickness direction, a drain layer positioned above the i-channel layer in the film thickness direction, an upper electrode layer positioned above the drain layer in the film thickness direction that forms a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is positioned closer to the drain layer than the source layer. Other apparatuses are described in accordance with more embodiments.
Vertical Steep-Slope Field-Effect Transistor (I-MOSFET) with Offset Gate Electrode for Driving a Perpendicular Magnetic Tunnel Junction (PMTJ)
According to one embodiment, an apparatus includes a bottom electrode layer positioned above a substrate in a film thickness direction, a source layer positioned above the bottom electrode layer in the film thickness direction, an impact ionization channel (i-channel) layer positioned above the source layer in the film thickness direction, a drain layer positioned above the i-channel layer in the film thickness direction, an upper electrode layer positioned above the drain layer in the film thickness direction that forms a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is positioned closer to the drain layer than the source layer. Other apparatuses are described in accordance with more embodiments.
Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ)
According to one embodiment, a method includes forming a bottom electrode layer above a substrate in a film thickness direction, forming a source layer above the bottom electrode layer in the film thickness direction, forming an impact ionization channel (i-channel) layer above the source layer in the film thickness direction, forming a drain layer above the i-channel layer in the film thickness direction, forming an upper electrode layer above the drain layer in the film thickness direction to form a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and forming a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is formed in a position closer to the drain layer than the source layer.
Quantum Doping Method and Use in Fabrication of Nanoscale Electronic Devices
A novel doping technology for semiconductor wafers has been developed, referred to as a quantum doping process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a quantized set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.