A nitride semiconductor device includes a substrate, a first electron transport layer above the substrate, a first electron supply layer above the first electron transport layer, a first nitride semiconductor layer above the first electron supply layer, a first opening passing through the first nitride semiconductor layer and the first electron supply layer and reaching the first electron transport layer, a second electron transport layer disposed above the first nitride semiconductor layer and along the inner surface of the first opening, a second electron supply layer disposed above the second electron transport layer and covering the first opening, a gate electrode disposed above the second electron supply layer and covering the first opening, a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, and a drain electrode.

The present disclosure provides an integrated circuit structure of a group III nitride semiconductor, a manufacturing method thereof, and use thereof. The integrated circuit structure is a complementary circuit of HEMT and HHMT based on the group III nitride semiconductor, and can realize the integration of HEMT and HHMT on the same substrate, and the HEMT and the HHMT respectively have a polarized junction with a vertical interface, the crystal orientations of the polarized junctions of the HEMT and the HHMT are different, the two-dimensional carrier gas forms a carrier channel in a direction parallel to the polarized junction, and corresponding channel carriers are almost depleted by burying the doped region. Compared with the conventional silicon-based CMOS, the integrated circuit structure of the present disclosure have advantages in aspects of carrier mobility, on-state current density, switching speed and so on, can realize low on-resistance, low parasitic inductance, and normally-off state of the device, and can achieve the technical effects of higher on-state current density, higher integration degree, and lower energy consumption.

Embodiments relate to the field of semiconductor technology, and propose a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a channel layer including a group III-V semiconductor and a group III-V semiconductor layer, the group III-V semiconductor and the group III-V semiconductor layer forming a heterojunction; a gate structure positioned on the channel layer, the gate structure including a gallium oxide layer, a gate oxide layer, and a gate electrode stacked in sequence; a source electrode positioned at an end of the heterojunction; and a drain electrode positioned at other end of the heterojunction.

A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.

A nitride semiconductor device includes a substrate, a drift layer and a block layer sequentially provided above the substrate, a gate opening penetrating through a block layer and reaching a drift layer, an electron transit layer and an electron supply layer sequentially provided above the block layer and along the inner surface of the gate opening, a gate electrode provided to cover the gate opening, a source opening penetrating through an electron supply layer and an electron transit layer and reaching the block layer, a source electrode provided in the source opening, and a drain electrode on the rear surface side of the substrate. Seen in a plan view, at least part of an outline of an end of the gate opening in the longitudinal direction follows an arc or an elliptical arc.

Embodiments are directed to high electron mobility transistor (HEMT) devices and methods. One such HEMT device includes a substrate having a first surface, and first and second heterostructures on the substrate and facing each other. Each of the first and second heterostructures includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. A doped semiconductor layer is disposed between the first and second heterostructures, and a source contact is disposed on the first heterostructure and the second heterostructure.

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.

There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising Al.sub.xGa.sub.1-xN, wherein 0≤x≤0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising Al.sub.yGa.sub.1-yN, wherein 0≤y≤0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.

The present disclosure provides a non-planar hole channel transistor and a fabrication method thereof. The non-planar hole channel transistor has a substrate, and a surface of the substrate has a step structure comprising a vertical surface. A non-planar channel layer is epitaxially grown laterally with the vertical surface as a core. A barrier layer is formed on the channel layer, so as to simultaneously form a two-dimensional hole gas and/or a two-dimensional electron gas at an interface between the barrier layer and the channel layer.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type; a second nitride semiconductor layer of a second conductivity type; an electron transport layer and an electron supply layer provided, in that order from a side on which the substrate is located, above the second nitride semiconductor layer and on an inner surface of a first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode provided in a second opening and connected to the second nitride semiconductor layer; a drain electrode; a third opening at an outermost edge part in a plan view of the substrate; and a potential fixing electrode provided in the third opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in contact with neither the electron transport layer nor the electron supply layer.