The object is to provide a semiconductor device that prevents a snapback operation and has excellent heat dissipation. The semiconductor device includes a semiconductor substrate, transistor portions, diode portions, a surface electrode, and external wiring. The transistor portions and the diode portions are provided in the semiconductor substrate and are arranged in one direction parallel with the surface of the semiconductor substrate. A bonding portion of the external wiring is connected to the surface electrode. The transistor portions and the diode portions are provided in a first region and a second region and alternately arranged in the one direction. A first transistor width and a first diode width in the first region are smaller than a width of the bonding portion. A second transistor width and a second diode width in the second region are larger than the width of the bonding portion.

A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.

A MOSFET having a stacked-gate super-junction design and novel termination structure. At least some illustrative embodiments of the device include a conductive (highly-doped with dopants of a first conductivity type) substrate with a lightly-doped epitaxial layer. The volume of the epitaxial layer is substantially filled with a charge compensation structure having vertical trenches forming intermediate mesas. The mesas are moderately doped via the trench sidewalls to have a second conductivity type, while the mesa tops are heavily-doped to have the first conductivity type. Sidewall layers are provided in the vertical trenches, the sidewall layers being a moderately-doped semiconductor of the first conductivity type. The shoulders of the sidewall layers are recessed below the mesa top to receive an overlying gate for controlling a channel between the mesa top and the sidewall layer. The mesa tops are coupled to a source electrode, while a drain electrode is provided on the back side of the substrate.

A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

Disclosed is a semiconductor device including a semiconductor layer having a main surface, a first conductivity type drift region formed at a surface layer part of the main surface, a super junction region having a first conductivity type first column region and a second conductivity type second column region, a second conductivity type low resistance region formed at the surface layer part of the drift region and having an impurity concentration in excess of that of the second column region, a region insulating layer formed on the main surface and covering the low resistance region such as to cause part of the low resistance region to be exposed, a first pad electrode formed on the region insulating layer such as to overlap with the low resistance region, and a second pad electrode formed on the main surface and electrically connected to the second column region and the low resistance region.

A semiconductor device includes a transistor cell with a source region of a first conductivity type and a gate electrode. The source region is formed in a wide bandgap semiconductor portion. A diode chain includes a plurality of diode structures. The diode structures are formed in the wide bandgap semiconductor portion and electrically connected in series. Each diode structure includes a cathode region of the first conductivity type and an anode region of a complementary second conductivity type. A gate metallization is electrically connected with the gate electrode and with a first one of the anode regions in the diode chain. A source electrode structure is electrically connected with the source region and with a last one of the cathode regions in the diode chain.

A silicon carbide MOSFET device that includes a silicon carbide substrate of a first dopant type; a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate; a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer; a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer; a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; and a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate. The first silicon carbide layer has lower doping than the silicon carbide substrate and defines a drift region. The third silicon carbide layer has higher doping than the first silicon carbide layer. The third silicon carbide layer includes a plurality of third portions that run substantially along a first direction. The second silicon carbide layer includes a plurality of second portions that run substantially along the first direction. The fourth silicon carbide layer includes a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction. The first and second directions each is parallel to the silicon carbide substrate. The transversely arranged P+ regions to N+ regions in some embodiments allow adequate P+ area to achieve good body diode performance and protection to the gate oxide, but without consuming significant area of the MOSFET cell.

An integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with a body diode of the MOSFET device. The monolithic diode device is configured so that a forward voltage drop Vf.sub.D2 of the monolithic diode device is less than a forward voltage drop Vf.sub.D1 of the body diode of the MOSFET device. The forward voltage drop Vf.sub.D2 is process tunable by controlling a gate oxide thickness, a channel length and body doping concentration level. The tunability of the forward voltage drop Vf.sub.D2 advantageously permits design of the integrated circuit to suit a wide range of applications according to requirements of switching speed and efficiency.

A method of forming a laterally varying dopant concentration profile of an electrically activated dopant in a power semiconductor device includes: providing a semiconductor body; implanting a dopant to form a doped region in the semiconductor body; providing, above the doped region, a mask layer having a first section and a second section, the first section having has a first thickness along a vertical direction and the second section having a second thickness along the vertical direction, the second thickness being different from the first thickness; and subjecting the doped region and both mask sections to a laser thermal annealing, LTA, processing step.