A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

A drive circuit includes a first driver to control on/off of an upper arm, a second driver to control on/off of a lower arm, a first switching device including a first terminal connected with a power supply for the first driver, a second terminal connected with a power supply for the second driver and a control terminal, a booster circuit to turn on the first switching device by boosting a control signal which is at a high level when the lower arm is in an on state, a second switching device to cause continuity between the control terminal and the booster circuit when the control signal is at the high level, and first switch unit to short-circuit the control terminal and the terminal for grounding when the control signal is at the low level.

A capacitor is provided for integration with a MOSFET device(s) formed on the same substrate. The capacitor comprises a first plate including a doped semiconductor layer of a first conductivity type, an insulating layer formed on an upper surface of the doped semiconductor layer, and a second plate including a polysilicon layer formed on an upper surface of the insulating layer. An inversion layer is formed in the doped semiconductor layer, beneath the insulating layer and proximate the upper surface of the doped semiconductor layer, as a function of an applied voltage between the first and second plates of the capacitor. At least one doped region of a second conductivity type, opposite the first conductivity type, is formed in the doped semiconductor layer adjacent to a drain and/or source region of the first conductivity type formed in the MOSFET device. The doped region is electrically connected to the inversion layer.

A semiconductor device package comprises a semiconductor switching device having a body, including a first side, and an opposing second side coupled to a substrate. A gate terminal is defined on the semiconductor switching device body first side, the gate terminal having a first side, and an opposing second side facing the semiconductor switching device body. A first gate resistor is disposed on the gate terminal first side, and coupled electrically in series with the gate terminal.

In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure.

A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and commonly connected to the first p-channel MISFET and the second p-channel MISFET, a first source conductor electrically connected to a source of the first p-channel MISFET, a second source conductor electrically connected to a source of the second p-channel MISFET, and a gate conductor electrically and commonly connected to a gate of the first p-channel MISFET and a gate of the second p-channel MISFET.

Various embodiments of the present disclosure provide a power device including at least one first conductive element adapted to generate a magnetic field when traversed by a current, and characterised in that it further comprises a Hall sensor electrically insulated from the first conductive element. The sensor and the first conductive element are mutually arranged so as to detect said magnetic field indicative of the current that traverses the first conductive element.

A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.

A semiconductor device polysilicon resistor formation method is provided. A third ion implantation and a fourth ion implantation are performed in a polysilicon resistor region, so that a high-resistance polysilicon resistor can be formed without an additional mask process.

An electronic device including semiconductor region located on a gallium nitride layer, two electrodes, located on either side of and insulated from the semiconductor region, the electrodes partially penetrating into the gallium nitride layer, and two lateral MOS transistors formed inside and on top of the semiconductor region.