To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

The present invention provides a self-healing field-effect transistor (FET) device comprising a self-healing substrate and a self-healing dielectric layer, said substrate and said layer comprising a disulfide-containing poly(urea-urethane) (PUU) polymer, wherein the dielectric layer has a thickness of less than about 10 μm, a gate electrode, at least one source electrode, and at least one drain electrode, said electrodes comprising electrically conductive elongated nanostructures; and at least one channel comprising semi-conducting elongated nanostructures. Further provided is a method for fabricating the FET device.

A display device and method of fabricating the same are provided. The display device includes a substrate and a thin-film transistor formed on the substrate. The thin-film transistor includes a lower gate conductive layer disposed on the substrate, and a lower gate insulating film disposed on the lower gate conductive layer The lower gate insulating film includes an upper surface and sidewalls. The thin-film transistor includes an active layer disposed on the upper surface of the lower gate insulating film, the active layer including sidewalls. At least one of the sidewalls of the lower gate insulating film and at least one of the sidewalls of the active layer are aligned with each other.

To provide a semiconductor device including a planar transistor having an oxide semiconductor and a capacitor. In a semiconductor device, a transistor includes an oxide semiconductor film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the gate electrode, a third insulating film over the second insulating film, and a source and a drain electrodes over the third insulating film; the source and the drain electrodes are electrically connected to the oxide semiconductor film; a capacitor includes a first and a second conductive films and the second insulating film; the first conductive film and the gate electrode are provided over the same surface; the second conductive film and the source and the drain electrodes are provided over the same surface; and the second insulting film is provided between the first and the second conductive films.

A transistor device including source and drain electrodes, a fin structure extending between and contacting respective sidewalls of the source and drain electrodes, a semiconductor channel layer over the upper surface and side surfaces of the fin structure and including a first and second vertical portions over the side surfaces of the fin structure, and the first and second vertical portions of the semiconductor channel layer both contact the respective sidewalls of the source electrode and the drain electrode, a gate dielectric layer over the semiconductor channel layer, and a gate electrode over the gate dielectric layer. By forming the semiconductor channel layer over a fin structure extending between sidewalls of the source and drain electrodes, a contact area between the semiconductor channel and the source and drain electrodes may be increased, which may provide increased driving current for the transistor device without increasing the device size.

A compound semiconductor has a high electron concentration of 5×10.sup.19 cm.sup.−3 or higher, exhibits an electron mobility of 46 cm.sup.2/V.Math.s or higher, and exhibits a low electric resistance, and thus is usable to produce a high performance semiconductor device. The present invention provides a group 13 nitride semiconductor of n-type conductivity that may be formed as a film on a substrate having a large area size at a temperature of room temperature to 700° C.

Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.

Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high E.sub.crit semiconductors are presented. A dielectric layer is deposited on a high E.sub.crit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high E.sub.crit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high E.sub.crit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.

IC devices with backend memory and electrical feedthrough networks of interconnects between the opposite sides of the IC devices, and associated assemblies, packages, and methods, are disclosed. An example IC device includes a back-side interconnect structure, comprising back-side interconnects; a frontend layer, comprising frontend transistors; a backend layer, comprising backend memory cells and backend interconnects; and a front-side interconnect structure, comprising front-side interconnects. In such an IC device, the frontend layer is between the back-side interconnect structure and the backend layer, the backend layer is between the frontend layer and the front-side interconnect structure, and at least one of the back-side interconnects is electrically coupled to at least one of the front-side interconnects by an electrical feedthrough network of two or more of the backend interconnects.

An integrated circuit (IC) device comprises a high voltage semiconductor device (HVSD) on a frontside of a semiconductor body and further comprises an electrode on a backside of the semiconductor body opposite the frontside. The HVSD may, for example, be a transistor or some other suitable type of semiconductor device. The electrode has one or more gaps directly beneath the HVSD. The one or more gaps enhance the effectiveness of the electrode for improving the breakdown voltage of the HVSD.