A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.

A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.

There is provided a copper bonding wire that exhibits a favorable bondability even when a scrub at the time of bonding is reduced. The copper bonding wire is characterized in that when a sum of percentages of Cu, Cu.sub.2O, CuO and Cu(OH).sub.2 on a surface of the wire as measured by X-ray Photoelectron Spectroscopy (XPS) is defined as 100%, Cu[II]/Cu[I] which is a ratio of a total percentage of CuO and Cu(OH).sub.2 (Cu[II]) corresponding to bivalent Cu to a percentage of Cu.sub.2O (Cu[I]) corresponding to monovalent Cu falls within a range from 0.8 to 12.

There is provided a copper bonding wire that exhibits a favorable bondability even when a scrub at the time of bonding is reduced. The copper bonding wire is characterized in that when a sum of percentages of Cu, Cu.sub.2O, CuO and Cu(OH).sub.2 on a surface of the wire as measured by X-ray Photoelectron Spectroscopy (XPS) is defined as 100%, Cu[II]/Cu[I] which is a ratio of a total percentage of CuO and Cu(OH).sub.2 (Cu[II]) corresponding to bivalent Cu to a percentage of Cu.sub.2O (Cu[I]) corresponding to monovalent Cu falls within a range from 0.8 to 12.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

A electronic module includes a printed circuit board (PCB) substrate, a controller substrate, a controller, a memory device, and a heat spreader. The controller is disposed on the controller substrate. The memory device is disposed on the PCB substrate. The heat spreader is disposed on the controller and the memory device, in which the heat spreader has a first portion on the controller and a second portion on the memory device, and the heat spreader has a first opening between the first portion and the second portion.

A electronic module includes a printed circuit board (PCB) substrate, a controller substrate, a controller, a memory device, and a heat spreader. The controller is disposed on the controller substrate. The memory device is disposed on the PCB substrate. The heat spreader is disposed on the controller and the memory device, in which the heat spreader has a first portion on the controller and a second portion on the memory device, and the heat spreader has a first opening between the first portion and the second portion.

A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a frame, the pad and the leads having a first thickness (115) and a first and an opposite and parallel second surface; the leads having a first portion (112) of first thickness near the gap and a second portion (111) of first thickness near the frame, and a zone (114) of reduced second thickness (116) between the first and second portions; the second surface (112a) of the first lead portions is coplanar with the second surface (111a) of the second portions. A semiconductor chip (220) with a terminal is attached the pad. A metallic wire connection (230) from the terminal to an adjacent lead includes a stitch bond (232) attached to the first surface of the lead.

A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a frame, the pad and the leads having a first thickness (115) and a first and an opposite and parallel second surface; the leads having a first portion (112) of first thickness near the gap and a second portion (111) of first thickness near the frame, and a zone (114) of reduced second thickness (116) between the first and second portions; the second surface (112a) of the first lead portions is coplanar with the second surface (111a) of the second portions. A semiconductor chip (220) with a terminal is attached the pad. A metallic wire connection (230) from the terminal to an adjacent lead includes a stitch bond (232) attached to the first surface of the lead.