A semiconductor package includes first semiconductor chips stacked on a package substrate, a lowermost first semiconductor chip of the first semiconductor chips including a recessed region, and a second semiconductor chip inserted in the recessed region, the second semiconductor chip being connected to the package substrate.

A display device includes a display panel including a display area and a non-display area defined therein and including a plurality of signal pads overlapping the non-display area, an electronic component including a base layer with an upper surface and a lower surface, a plurality of driving pads disposed on the lower surface of the base layer, and a plurality of driving bumps respectively disposed on the plurality of driving pads, the plurality of driving bumps being respectively connected to the signal pads, and a filler disposed between the display panel and the electronic component. A first hole is defined in the upper surface of the base layer, and the first hole does not overlap the plurality of driving bumps in a plan view.

A semiconductor package includes a substrate extending in a first direction and a second direction perpendicular to the first direction, a first semiconductor chip disposed on the substrate, the first semiconductor chip having a stepped portion, a second semiconductor chip disposed on the substrate and horizontally spaced apart from the first semiconductor chip in the first direction, a third semiconductor chip disposed on the second semiconductor chip and a bottom surface of the stepped portion, and an upper adhesive layer disposed between the second semiconductor chip and the third semiconductor chip, the upper adhesive layer contacting a portion of the bottom surface of the stepped portion.

A semiconductor package includes a circuit board including a wiring structure, first and second semiconductor chips disposed on the circuit board and connected to the wiring structure, a dummy chip disposed on the circuit board and positioned between the first and second semiconductor chips, and a molded member disposed on the circuit board and surrounding the first and second semiconductor chips and the dummy chip. The dummy chip may include a rounded edge between an upper surface and a side surface.

The present disclosure describes a process for making a three-dimensional (3D) package, which starts with providing a mold precursor module that includes a first device die and a floor connectivity die (FCD) encapsulated by a mold compound. The FCD includes a sacrificial die body and multiple floor interconnections underneath the sacrificial die body. Next, the mold compound is thinned down until the sacrificial die body of the FCD is completely consumed, such that each floor interconnection is exposed through the mold compound. The thinning down step does not affect a device layer in the first device die. A second device die, which includes a die body and multiple electrical die interconnections, is then mounted over the exposed floor interconnections. Herein, each electrical die interconnection is vertically aligned with and electrically connected to a corresponding floor interconnection from the FCD.

The first logic wafer is attached to a supporting wafer, which adds sufficient depth to this bonded structure such that the first logic wafer may be thinned during the manufacturing process. The first logic wafer is thinned such that the through silicon vias may be etched in the substrate of the first logic wafer so as to provide adequate connectivity to a second logic wafer, which is bonded to the first logic wafer. The second logic wafer adds sufficient depth to this bonded structure to allow the supporting wafer to then be thinned to enable through silicon vias to be added to the supporting wafer so as to provide appropriate connectivity for the entire stacked structure. The thinned supporting wafer is retained in the finished stacked wafer structure and may comprise additional components (e.g. capacitors) supporting the operation of the processing circuitry in the logic wafers.

Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes dielectric layers, a conductive layer disposed in the dielectric layers, and a via layer disposed in the dielectric layers proximate the conductive layer. An underball metallization (UBM) layer is disposed in the dielectric layers proximate the via layer. A first connector coupling region is disposed in the via layer and the UBM layer. A via layer portion of the first connector coupling region is coupled to a first contact pad in the conductive layer. A second connector coupling region is disposed in the UBM layer. The second connector coupling region is coupled to a conductive segment in the UBM layer and the via layer. The second connector coupling region is coupled to a second contact pad in the conductive layer by the conductive segment.

A semiconductor device includes a first heat sink formed in contact with a back surface of a first semiconductor chip, and a second heat sink formed in contact with a back surface of a second semiconductor chip. The first heat sink is made of a material with larger thermal conductivity than that of the first semiconductor chip and has a heat dissipation surface exposed from the mold resin layer to the outside. The second heat sink is made of a material with larger thermal conductivity than that of the second semiconductor chip and has a heat dissipation surface exposed from the mold resin layer to the outside.

A semiconductor device includes: a semiconductor base body; a semiconductor chip; a sintering material layer bonded to a lower surface of the semiconductor chip and having a thickness decreasing toward an outer periphery of the semiconductor chip; and a conductive plate having a main surface facing the lower surface of the semiconductor chip and a recessed portion which the sintering material layer contacts in the main surface, the recessed portion having a depth decreasing toward the outer periphery of the semiconductor chip.

A method for manufacturing a semiconductor device includes a step of preparing a semiconductor substrate that has a first main surface on one side and a second main surface on the other side, the semiconductor substrate on which a plurality of device forming regions and an intended cutting line that demarcates the plurality of device forming regions are set, a step of forming a first electrode that covers the first main surface in each of the device forming regions, a step of forming a second electrode that covers the second main surface, a step of partially removing the second electrode along the intended cutting line such that the semiconductor substrate is exposed, and forming a removed portion that extends along the intended cutting line, and a step of cutting the semiconductor substrate along the removed portion.