A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.

Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.

A semiconductor device in which occurrence of peeling between a filling member and a metal terminal is suppressed is obtained. The semiconductor device includes: an insulating substrate having a front surface and a back surface, and having a semiconductor element joined to the front surface; a base plate joined to the back surface of insulating substrate; a case member surrounding insulating substrate; a filling member having an upper surface, covering insulating substrate, and filling a region surrounded by base plate and case member; and a metal member having a plate shape that leans toward an upper surface side of filling member inside filling member, has one end joined to the front surface of insulating substrate and another end separated from an inner wall of case member, and is exposed from the upper surface of filling member.

A semiconductor device includes: a metal block; a semiconductor element fixed to an upper surface of the block with a first joining material; a main terminal fixed to an upper surface of the element with a second joining material; a signal terminal electrically connected to the element; and a mold resin covers the element, the first and second joining materials, a part of the block, of the main and signal terminals. In the element, a current flows in a longitudinal direction. A lower surface of the block is exposed from the resin. The main and the signal terminals are exposed from a side surface of the resin. The main terminal has a first portion in the resin, a second portion continuous with the first portion and bent downward outside the resin, and a third portion continuous with the second portion and substantially parallel to a lower surface of the resin.

An object is to provide a technique capable of improving the power efficiency of a semiconductor device. The semiconductor device includes first to sixth parallel connection bodies, each including a semiconductor switching element and a diode connected in antiparallel to the semiconductor switching element. At least one of the voltage drops of the second parallel connection body and the third parallel connection body is smaller than a voltage drop of at least one of the first parallel connection body, the fourth parallel connection body, the fifth parallel connection body, and the sixth parallel connection body.

Provided are a resin composition for encapsulation that is superior in high-temperature reverse bias test (HTRB test) reliability; and a semiconductor device. The resin composition for encapsulation is used to encapsulate a power semiconductor element made of Si, SiC, GaN, Ga.sub.2O.sub.3 or diamond, and a cured product of the resin composition for encapsulation has a dielectric tangent of not larger than 0.50 when measured at 150° C. and 0.1 Hz. The semiconductor device is such that a power semiconductor element made of Si, SiC, GaN, Ga.sub.2O.sub.3 or diamond is encapsulated by the cured product of the resin composition for encapsulation.

A semiconductor module includes: a case; a semiconductor chip provided inside the case; a seal material injected to inside of the case and sealing the semiconductor chip; and a lid provided inside the case and contacting an upper surface of the seal material, wherein a tapered portion is provided at an end portion of the lid on an upper surface side, a gap is provided between a side surface of the end portion of the lid and an inner side surface of the case, and the seal material crawls up to the tapered portion through the gap.

In a semiconductor device, a semiconductor element includes a semiconductor substrate, a surface electrode and a protective film. The semiconductor substrate has an active region and an outer peripheral region. The surface electrode includes a base electrode disposed on a front surface of the semiconductor substrate and a connection electrode disposed on the base electrode. The protective film covers a peripheral end portion of the base electrode and an outer peripheral edge of the connection electrode. The protective film has an opening to expose the connection electrode so as to enable a solder connection. A boundary between the outer peripheral edge of the connection electrode and the protective film is located at a position corresponding to the outer peripheral region in a plan view.

A semiconductor device package includes a substrate, a silicon (Si) or silicon carbide (SiC) semiconductor die, and a metal layer on a surface of the semiconductor die. The metal layer includes a bonding surface that is attached to a surface of the substrate by a die attach material. The bonding surface includes opposing edges that extend along a perimeter of the semiconductor die, and one or more non-orthogonal corners that are configured to reduce stress at an interface between the bonding surface and the die attach material. Related devices and fabrication methods are also discussed.