Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.

An object of the present invention is to provide an electrically conductive paste and a sintered body thereof having a low electric resistance value and excellent electrical conductivity when made into a sintered body. An electrically conductive paste comprising: a flake-like silver powder having a median diameter D50 of 15 μm or less; a silver powder having a median diameter D50 of 25 μm or more; and a solvent, wherein the content of the flake-like silver powder is 15 to 70 parts by mass and the content of the silver powder having a median diameter D50 of 25 μm or more is 30 to 85 parts by mass based on 100 parts by mass in total of the flake-like silver powder and the silver powder having a median diameter D50 of 25 μm or more.

In an optical receiver circuit which suppresses an unnecessary increase in impedance and occurrences of resonance and radiation noise and which produces preferable high-frequency transmission characteristics, a PD submount mounted with a PD chip and a chip capacitor and a TIA carrier mounted with a TIA chip are electrically connected to each other by a bonding wire. The chip includes an anode electrode pad and a cathode electrode pad, anode electrode-side ground pads are formed at positions that sandwich the pad, and cathode electrode-side ground pads are formed at positions that sandwich the pad. A wire electrically connects the pad and a signal pad for input of the chip to each other, a wire electrically connects the pad and the capacitor to each other, and a wire electrically connects the pads and the pads to each other.

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.

The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.

An electronic apparatus including a substrate, a plurality of first bonding pads, an electronic device, and a first spacer is provided. The first bonding pads are disposed on the substrate. The electronic device is disposed on the substrate and electrically connected to the first bonding pads. The first spacer is disposed between the electronic device and the substrate. The electronic device is capable of effectively controlling a height and uniformity of a gap between the electronic device and the substrate, so as to prevent the electronic device from being tilted and ensure the electronic device to have a favorable structural reliability.

An electronics assembly includes a plurality of planar conductive metal sheets including a first conductive metal sheet, a second conductive metal sheet attached and electrically coupled to the first metal sheet, and a third conductive metal sheet attached and electrically coupled to the second metal sheet. The second metal sheet is located between the first and third conductive metal sheets. Air gaps are defined in the plurality of planar conductive metal sheets to form metal traces that define electrically isolated conductive paths from an outer surface of the first conductive metal sheet to an outer surface of the third conductive metal sheet in a multilevel conductive wiring network. The multilevel conductive wiring network can be attached and electrically coupled to a microchip and to one or more capacitors to form a power converter.

A semiconductor device includes: a conductive base substrate; a semiconductor chip mounted on the base substrate and having a signal pad; a frame configured to surround the semiconductor chip, to be mounted on the base substrate, and to include a step having an inner first upper surface and an outer second upper surface higher than the first upper surface in a plan view, wherein a first conductor pattern provided on the first upper surface is electrically connected to the base substrate; a capacitive component mounted on the first conductor pattern; a signal terminal mounted on the second upper surface of the frame; a first bonding wire configured to electrically connect the signal pad and an upper surface of the capacitive component; and a second bonding wire configured to electrically connect the upper surface of the capacitive component and the signal terminal.

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost.