Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.

An object of the present invention is to provide an electrically conductive paste and a sintered body thereof having a low electric resistance value and excellent electrical conductivity when made into a sintered body. An electrically conductive paste comprising: a flake-like silver powder having a median diameter D50 of 15 μm or less; a silver powder having a median diameter D50 of 25 μm or more; and a solvent, wherein the content of the flake-like silver powder is 15 to 70 parts by mass and the content of the silver powder having a median diameter D50 of 25 μm or more is 30 to 85 parts by mass based on 100 parts by mass in total of the flake-like silver powder and the silver powder having a median diameter D50 of 25 μm or more.

A semiconductor device package comprises a semiconductor switching device having a body, including a first side, and an opposing second side coupled to a substrate. A gate terminal is defined on the semiconductor switching device body first side, the gate terminal having a first side, and an opposing second side facing the semiconductor switching device body. A first gate resistor is disposed on the gate terminal first side, and coupled electrically in series with the gate terminal.

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.

The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.

A semiconductor device includes first semiconductor chips that each include a first control electrode and a first output electrode, second semiconductor chips each include a second control electrode and a second output electrode, first and second input circuit patterns on which the first and second input electrodes are disposed, respectively, first and second control circuit patterns electrically connected to the first and second control electrodes, respectively, first and second resistive elements, and a first inter-board wiring member. The first control electrodes and first resistive element are electrically connected via the first control circuit pattern, the second control electrodes and second resistive element are electrically connected via the second control circuit pattern, and at least one of the first output electrodes and at least one of the second output electrodes are electrically connected to each other via the first inter-board wiring member.

An electronic apparatus including a substrate, a plurality of first bonding pads, an electronic device, and a first spacer is provided. The first bonding pads are disposed on the substrate. The electronic device is disposed on the substrate and electrically connected to the first bonding pads. The first spacer is disposed between the electronic device and the substrate. The electronic device is capable of effectively controlling a height and uniformity of a gap between the electronic device and the substrate, so as to prevent the electronic device from being tilted and ensure the electronic device to have a favorable structural reliability.

A transistor package that includes a metal submount; a transistor die mounted on said metal submount; a surface mount IPD component that includes a dielectric substrate; and the dielectric substrate mounted on said metal submount. Additionally, the dielectric substrate includes one of the following: an irregular shape, a non-square shape, and a nonrectangular shape.

A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.