An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an p-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.

An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.

A spacer system for a semiconductor switching device which is formed as a spacer ring and a plurality of insulating elements and supporting elements are arranged in an alternating manner around a circumference of the spacer ring. The insulating element includes a recess receiving a cathode gate connector element. The supporting element includes a projection receiving a spring system for clamping while assembling the switching device. The switching device includes a substrate, a cathode pole piece, an anode pole piece, strain buffer plates and a gate ring. Further connector elements, are electrically connecting the cathode pole piece and the gate ring of the semiconductor switching device to an external circuit unit. The space between the connector elements is minimized in order to reduce the gate circuit impedance, thus enabling an increased maximum turn-off current and further allowing for the use of larger semiconductor switching devices for high power applications.