A semiconductor package includes a semiconductor chip including an electrode pad formed on the top surface thereof, a passive device embedded in the semiconductor package, the passive device having no functional electrode on the top surface thereof, a cover layer covering the semiconductor chip and the passive device, and at least one electrode pattern formed on the cover layer to transmit electrical signals. The cover layer includes at least one first opening formed to expose a region in which the functional electrode is to be formed. The electrode pattern includes a functional electrode portion formed in a region in which the functional electrode of the passive device is to be formed through the first opening. In the process of forming the electrode pattern, a functional electrode of the passive device is formed together therewith, thereby eliminating a separate step of manufacturing a functional electrode and thus reducing manufacturing costs.

An optical module includes an optical semiconductor chip including a first electrode pad, a second electrode pad, and a third electrode pad arranged between the first electrode pad and the second electrode pad, a wiring substrate on which the optical semiconductor chip is flip-chip mounted, including a fourth electrode pad, a fifth electrode pad, and a sixth electrode pad arranged between the fourth electrode pad and the fifth electrode pad, a first conductive material connecting the first electrode pad with the fourth electrode pad, a second conductive material connecting the second electrode pad with the fifth electrode pad, a third conductive material arranged between the first conductive material and the second conductive material, connecting the third electrode pad with the sixth electrode pad, and a resin provided in an area on the second conductive material side of the third conductive material between the optical semiconductor chip and the wiring substrate.

A packaged integrated circuit includes a core structure with a cavity therein; a component accommodated in the cavity; an electrically insulating structure formed over the core structure and the component; a partially electrically insulating carrier structure formed below the core structure and the component; and an electrically conducting redistribution arrangement formed at least partially within the carrier structure. The redistribution arrangement includes conductor structures each having a first element extending through the carrier structure and electrically connecting a contact of the component and a second element below the carrier structure. A part of the second element is a contact pad for electrically connecting the redistribution arrangement with external circuitry. The carrier structure includes a polyimide layer and an adhesive layer. The adhesive layer is directly attached to an upper surface of the polyimide layer and to a lower surface of the core structure and a lower surface of the component.

An integrated circuit package includes a transmission line structure, wire bonds, a first post and a second post. The transmission line structure runs from a printed circuit board (PCB) to an integrated circuit (IC) and includes a center transmission line between two ground lines and sealed from exposure to air. The wire bonds connect the transmission line structure to pads on the integrated circuit from where the center transmission line exits the integrated circuit package. The wire bonds are selected to have an impedance matched to impedance of the integrated circuit. The first post supports the center transmission line where the center transmission line enters the integrated circuit package from the printed circuit board. The second post supports the center transmission line where the center transmission line exits the integrated circuit package to connect to the wire bonds.

An electronic device including a connection element is provided. The connection element includes a first insulation layer and a second insulation layer. The first insulation layer has a first opening. A sidewall of the first insulation layer at the first opening has roughness different from roughness of a top surface of the first insulation layer. The second insulation layer is disposed on the first insulation layer, and the second insulation layer has a second opening. The sidewall of the first insulation layer at the first opening is exposed by the second opening. A method of fabricating an electronic device is also provided.

A method of collective fabrication of 3D electronic modules, each 3D electronic module comprising a stack of at least two, surface transferable, ball grid electronic packages, tested at their operating temperature and frequency comprises: a step of fabricating reconstituted wafers, each reconstituted wafer being fabricated according to the following sub-steps in the following order: A1)) the electronic packages are placed on a first sticky skin, balls side, B1) molding of the electronic packages in the resin and polymerization of the resin, to obtain the intermediate wafer, C1) thinning of the intermediate wafer on the face of the intermediate wafer opposite to the balls, D1) removal of the first sticky skin and placing of the intermediate wafer on a second sticky skin, side opposite to the balls, E1) thinning of the intermediate wafer on the balls side face, F1) formation of a balls side redistribution layer, G1) removal of the second sticky skin to obtain a reconstituted wafer of smaller thickness than the original thickness of the electronic packages, several reconstituted wafers having been obtained on completion of the previous sub-steps, stacking of the reconstituted wafers, dicing of the stacked reconstituted wafers to obtain 3D modules.

A multilayer wiring board includes a first insulating layer, a second insulating layer stacked on the first insulating layer, a via conductor inside each of the first insulating layer and the second insulating layer, and a conductive bonding layer that bonds the via conductors to each other. The first insulating layer is directly bonded to the second insulating layer, and a relationship a.sub.1>b.sub.1 is satisfied, where a.sub.1 is a maximum diameter of the bonding layer and b.sub.1 is a maximum diameter of the via conductor at an interface with the bonding layer.

A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack disposed on the first surface of the carrier substrate. The chip stack includes a first semiconductor die, a second semiconductor die, and an interposer between the first semiconductor die and the second semiconductor die. The interposer transmits signals between the first semiconductor die and the second semiconductor die.

A semiconductor chip is mounted on a mounting substrate. The semiconductor chip includes plural first bumps on a surface facing the mounting substrate. The plural first bumps each have a shape elongated in a first direction in plan view and are arranged in a second direction perpendicular to the first direction. The mounting substrate includes, on a surface on which the semiconductor chip is mounted, at least one first land connected to the plural first bumps. At least two first bumps of the plural first bumps are connected to each first land. The difference between the dimension of the first land in the second direction and the distance between the outer edges of two first bumps at respective ends of the arranged first bumps connected to the first land is 20 μm or less.

An apparatus includes: a transistor including an input terminal for an input signal and an output terminal for an output signal; a matching circuit configured to match a load impedance regarding a fundamental harmonic of at least one of the input signal and the output signal to an impedance of the transistor and include a first conductive film being laminated over the transistor and coupled to at least one of the input terminal and the output terminal; and a processing circuit configured to adjust an impedance regarding a harmonic of at least one of the input signal and the output signal and include a second conductive film being laminated over the first conductive film and coupled to at least one of the input terminal and the output terminal through a via which penetrates through a dielectric layer sandwiched between the first conductive film and the second conductive film.