An electronic device includes a multilevel package substrate with first, second, third, and fourth levels, a semiconductor die mounted to the first level, and a conductor backed coplanar waveguide transmission line feed with an interconnect and a conductor, the interconnect including coplanar first, second, and third conductive lines extending in the first level along a first direction from respective ends to an antenna, the second and third conductive lines spaced apart from opposite sides of the first conductive line along an orthogonal second direction, and the conductor extending in the third level under the interconnect and under the antenna.

Shielded radio-frequency (RF) module having reduced area. In some embodiments, a method for fabricating a radio-frequency module includes forming or providing a packaging substrate configured to receive a plurality of components. The method may include mounting one or more devices on the packaging substrate such that the packaging substrate includes a first area associated with mounting of each of the one or more devices. In some embodiments, the method further includes forming a plurality of shielding wirebonds on the packaging substrate to provide RF shielding functionality for one or more regions on the packaging substrate, such that the packaging substrate includes a second area associated with formation of each shielding wirebond, the mounting of each device implemented with respect to a corresponding shielding wirebond such that a portion of the first area associated with the device overlaps at least partially with a portion of the second area associated with the corresponding shielding wirebond.

A manufacturing method of a mounting structure includes: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member; a disposing step of disposing a thermosetting sheet and a thermoplastic sheet on the mounting member, with the thermosetting sheet interposed between the thermoplastic sheet and the first circuit member; a first sealing step of pressing a stack of the thermosetting sheet and the thermoplastic sheet against the first circuit member, and heating the stack, to seal the second circuit members and to cure the thermosetting sheet into a cured layer; and a removal step of removing the thermoplastic sheet from the cured layer. At least one of the second circuit members is a hollow member having a space from the first circuit member, and in the first sealing step, the second circuit members are sealed so as to maintain the space.

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

A device includes an integrated circuit, a first seal ring, a second seal ring, and a dielectric layer. The first seal ring surrounds the integrated circuit and includes a plurality of first seal portions separated from each other by a plurality of first gaps. The second seal ring surrounds the integrated circuit, between the integrated circuit and the first seal ring and includes a plurality of second seal portions separated from each other by a plurality of second gaps. The dielectric layer surrounds the first and second seal rings and includes a plurality of first filling portions in the first gaps, respectively, and a plurality of second filling portions in the second gaps, respectively. A connection line of one of the first filling portions and one of the second filling portions closest to said one of the first filling portions is not parallel to edges of the integrated circuit.

An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

Power amplifier electronics for controlling application of radio frequency (RF) energy generated using solid state electronic components may further be configured to control application of RF energy in cycles between high and low powers. The power amplifier electronics may include a semiconductor die on which one or more RF power transistors are fabricated, an output matching network configured to provide impedance matching between the semiconductor die and external components operably coupled to an output tab, and bonding ribbon bonded at terminal ends thereof to operably couple the one or more RF power transistors of the semiconductor die to the output matching network. The bonding ribbon may have a width of greater than about five times a thickness of the bonding ribbon.

A high frequency circuit includes: a first wire provided on a front surface of a board and being in contact with a heat generation part; a second wire provided on the front surface of the board and connected to ground; and a chip resistor connected between the first wire and the second wire and having a thermal conductive characteristic and an electric insulation characteristic, and the first wire includes: a wire part which is disposed between the heat generation part and the chip resistor, and which has a characteristic impedance equal to an impedance as a reference for impedance matching in the first wire; and a wire part which is disposed on a low temperature side with the chip resistor being set as a boundary, and which has a thermal resistance higher than that of the chip resistor.

An antenna module includes a ground layer including a through-hole; a feed via disposed to pass through the through-hole; a patch antenna pattern spaced apart from the ground layer and electrically connected to one end of the feed via; a coupling patch pattern spaced apart from the patch antenna pattern; a first dielectric layer to accommodate the patch antenna pattern and the coupling patch pattern; a second dielectric layer to accommodate at least a portion of the feed via and the ground layer; and electrical connection structures disposed between the first dielectric layer and the second dielectric layer to separate the first dielectric layer from the second dielectric layer.

A method of transferring a micro device and an array of micro devices are disclosed. A carrier substrate carrying a micro device connected to a bonding layer is heated to a temperature below a liquidus temperature of the bonding layer, and a transfer head is heated to a temperature above the liquidus temperature of the bonding layer. Upon contacting the micro device with the transfer head, the heat from the transfer head transfers into the bonding layer to at least partially melt the bonding layer. A voltage applied to the transfer head creates a grip force which picks up the micro device from the carrier substrate.