Provided is a power semiconductor module that can secure insulating properties. A semiconductor element is mounted on a resin-insulated base plate including a circuit pattern, a resin insulating layer, and a base plate. A case enclosing the resin-insulated base plate is bonded to the resin insulating layer with an adhesive. The resin insulating layer and the case are bonded together with a region enclosed by the resin insulating layer and a tapered portion of the case formed closer to the resin insulating layer being filled with the adhesive made of a material identical to that of the sealing resin. Air bubbles in the adhesive appear in the tapered portion opposite to the resin insulating layer.

Embodiments may relate to a method of forming a microelectronic package with an integrated heat spreader (IHS). The method may include placing a solder thermal interface material (STIM) layer on a face of a die that is coupled with a package substrate; coupling the IHS with the STIM layer and the package substrate such that the STIM is between the IHS and the die; performing formic acid fluxing of the IHS, STIM layer, and die; and dispensing, subsequent to the formic acid fluxing, sealant on the package substrate around a periphery of the IHS.

There are provided a semiconductor module capable of preventing the peeling of a sealing resin on the side where a connection section used for the connection to a semiconductor element is arranged and a manufacturing method for a semiconductor module. A semiconductor module includes: an outer frame; sealing resins; gate signal output terminals, and partition sections laid across the outer flame to partition a space into a plurality of housing sections, in the partition sections which the gate signal output terminals with connection sections exposed are arranged. The partition sections have through holes where sealing resins are formed, the sealing resins connecting adjacent housing sections and the sealing resin formed in the through hole being continuous with the sealing resins formed in the housing sections.

A semiconductor device includes a semiconductor element, at least one first resin member, and at least one conducting wire. The semiconductor element includes a front electrode and a body part. The at least one first resin member is disposed on a second surface of the front electrode. The at least one conducting wire includes a joining part. The at least one first resin member includes a convex part. The convex part protrudes from the front electrode in a direction away from the body part. The at least one conducting wire includes a concave part. The concave part is adjacent to the joining part. The concave part extends along the convex part. The concave part is fitted to the convex part.

A light source device includes a substrate, an electrode layer and an annular step-like surrounding frame both disposed on the substrate, a light emitter and a light detector both spaced apart from each other and mounted on the electrode layer in the surrounding frame, and a light permeable member disposed on the surrounding frame. The surrounding frame includes an upper tread arranged away from the substrate, an upper riser connected to an inner edge of the upper tread, a lower tread arranged at an inner side of the upper riser, and a lower riser connected to an inner edge of the lower tread and arranged away from the upper tread. The surrounding frame has a notch recessed in the lower tread and the lower riser for spatially communicating an inner side of the surrounding frame to an external space.

An air cavity package with one or more dovetail recesses configured with a first recess and a coincident second recess. The first recess has a first depth and the second recess has a second depth. The first recess has a lower width and an upper width smaller than the first lower width creating a dovetail shape. Individual dovetail recesses are created by creating a first recess in the flange at a first width and depth. A second recess with a second width and second depth and coincident with the first recess is pressed into the flange. The second width is greater than the first width and the second depth is smaller than the first depth. Pressing the second recess causes the first width at an upper portion to decrease, causing the first recess to develop a dovetail shape.

Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame may include a plurality of lead sets, each lead set including leads having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. A mold chase may be applied to the plating surfaces, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface. The lead frame assembly may be partially embedded in a mold encapsulation such that portions of the mold encapsulation contact the peak surfaces. The mold chase may be removed to expose the vias containing sidewalls and the plating surfaces and the sidewalls may be plated with an electrical plating.

Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame may include a plurality of lead sets, each lead set including leads having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. A mold chase may be applied to the plating surfaces, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface. The lead frame assembly may be partially embedded in a mold encapsulation such that portions of the mold encapsulation contact the peak surfaces. The mold chase may be removed to expose the vias containing sidewalls and the plating surfaces and the sidewalls may be plated with an electrical plating.

Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.