Patent classifications
H01L2924/17763
Chip package and a wafer level package
Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.
CHIP PACKAGE AND A WAFER LEVEL PACKAGE
Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.
Encapsulating resin composition, semiconductor device using the encapsulating resin composition, and method for manufacturing semiconductor device using the encapsulating resin composition
An encapsulating resin composition contains a thermosetting resin component, a curing accelerator, an inorganic filler, an ion trapping agent, and an aromatic monocarboxylic acid having one or more electron-withdrawing functional groups selected from a nitro group and a cyano group. The encapsulating resin composition is solid at 25 C., and has a sulfur content, measured by X-ray fluorescence analysis, of 0.1 mass % or less in terms of SO.sub.3.
Chip package and a wafer level package
Various embodiments provide for a chip package consisting of a layer over a carrier, further carrier material over the layer, wherein one or more portions of the further carrier material is removed, and a chip with one or more contact pads, where the chip is adhered to the carrier via the layer. A wafer level package consisting of a plurality of chips adhered to the carrier via a plurality of portions of the layer released from the further carrier material is also provided for.