A semiconductor device manufacturing method includes a molding step including disposing a control pin between an inlet and a control wire and on a line connecting the inlet and the control wire in a plan view of the semiconductor device, injecting molding resin raw material into a cavity through the inlet, filling the cavity with the molding resin raw material, and sealing a semiconductor chip and a control element disposed on a main current lead frame and a control lead frame. In this way, the flow velocity of the molding resin raw material flowing to the control wire is reduced.

A semiconductor device manufacturing method includes a molding step including disposing a control pin between an inlet and a control wire and on a line connecting the inlet and the control wire in a plan view of the semiconductor device, injecting molding resin raw material into a cavity through the inlet, filling the cavity with the molding resin raw material, and sealing a semiconductor chip and a control element disposed on a main current lead frame and a control lead frame. In this way, the flow velocity of the molding resin raw material flowing to the control wire is reduced.

A circuit for sensing a current comprises a substrate having a first and a second major surface, the second major surface being opposite to the first major surface. At least one magnetic field sensing element is arranged on the first major surface of the substrate and is suitable for sensing a magnetic field caused by a current flow in a current conductor coupled to the second major surface. The substrate also comprises at least one insulation layer, substantially buried between the first major surface and the second major surface of the substrate.

A circuit for sensing a current comprises a substrate having a first and a second major surface, the second major surface being opposite to the first major surface. At least one magnetic field sensing element is arranged on the first major surface of the substrate and is suitable for sensing a magnetic field caused by a current flow in a current conductor coupled to the second major surface. The substrate also comprises at least one insulation layer, substantially buried between the first major surface and the second major surface of the substrate.

An object of the present disclosure is to provide a trench gate type power semiconductor device that does not easily break even when stress is applied. A SiC-MOSFET includes a SiC substrate, a drift layer of a first conductive type, formed on the SiC substrate, a base region of a second conductivity type formed in a surface layer of the drift layer, a source region of the first conductivity type selectively formed in a surface layer of the base region, a trench extending through the base region and the source region and reaching the drift layer, a gate electrode embedded in the trench and having a V-shaped groove on an upper surface thereof, and an oxide film formed on an upper surface including the groove of the gate electrode, in which a bottom of the V-shape groove is deeper than the base region.

An object of the present disclosure is to provide a trench gate type power semiconductor device that does not easily break even when stress is applied. A SiC-MOSFET includes a SiC substrate, a drift layer of a first conductive type, formed on the SiC substrate, a base region of a second conductivity type formed in a surface layer of the drift layer, a source region of the first conductivity type selectively formed in a surface layer of the base region, a trench extending through the base region and the source region and reaching the drift layer, a gate electrode embedded in the trench and having a V-shaped groove on an upper surface thereof, and an oxide film formed on an upper surface including the groove of the gate electrode, in which a bottom of the V-shape groove is deeper than the base region.

A semiconductor device includes a substrate, a conductive part, a controller module and a sealing resin. The substrate has a substrate obverse surface and a substrate reverse surface facing away from each other in a z direction. The conductive part is made of an electrically conductive material on the substrate obverse surface. The controller module is disposed on the substrate obverse surface and electrically connected to the conductive part. The sealing resin covers the controller module and at least a portion of the substrate. The conductive part includes an overlapping wiring trace having an overlapping portion overlapping with the electronic component as viewed in the z direction. The overlapping portion of the overlapping wiring trace is not electrically bonded to the controller module.

A semiconductor device includes a substrate, a conductive part, a controller module and a sealing resin. The substrate has a substrate obverse surface and a substrate reverse surface facing away from each other in a z direction. The conductive part is made of an electrically conductive material on the substrate obverse surface. The controller module is disposed on the substrate obverse surface and electrically connected to the conductive part. The sealing resin covers the controller module and at least a portion of the substrate. The conductive part includes an overlapping wiring trace having an overlapping portion overlapping with the electronic component as viewed in the z direction. The overlapping portion of the overlapping wiring trace is not electrically bonded to the controller module.

Provided is a metal component that is configured to be used for manufacturing a semiconductor device, the metal component including: a substrate having a conductivity; and a noble metal plating layer formed on all or part of a surface of the substrate, wherein the noble metal plating layer has a surface with irregularities, and a protrusion of the irregularities has an aspect ratio of 0.3 or more.

Provided is a metal component that is configured to be used for manufacturing a semiconductor device, the metal component including: a substrate having a conductivity; and a noble metal plating layer formed on all or part of a surface of the substrate, wherein the noble metal plating layer has a surface with irregularities, and a protrusion of the irregularities has an aspect ratio of 0.3 or more.