To provide a circuit module capable of suppressing a decrease in an area for mounting an electronic component on a substrate even when a wire for shielding the electronic component is connected to the substrate. A circuit module according to the present disclosure includes a substrate, a first component mounted on the substrate and including a ground terminal on an upper surface, first wires that connect the ground terminal to the substrate, and a second component mounted on the substrate, in which overlapping first wires in plan view.

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate and a first passive device. The substrate has a first surface and a second surface opposite to the first surface. The first passive device includes a first terminal and a second terminal, wherein the first terminal is closer to the first surface than to the second surface, and the second terminal is closer to the second surface than to the first surface.

A semiconductor package includes a package substrate including a base substrate including a redistribution layer, pads disposed on first and second surfaces of the base substrate and connected to the redistribution layer, and a protective layer having a mounting region in which first openings respectively exposing first pads among the pads and a second opening exposing second pads among the pads and a portion of the second surface are disposed on the second surface; a semiconductor chip disposed on the mounting region and connected to the pads through the first openings and the second opening; and a sealing material covering a portion of the semiconductor chip and extending into the second opening. Four first openings among the first openings are respectively disposed adjacent to respective corners of the mounting region. The second opening is disposed to divide the four first openings into at least two groups.

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate and a first passive device. The substrate has a first surface and a second surface opposite to the first surface. The first passive device includes a first terminal and a second terminal, wherein the first terminal is closer to the first surface than to the second surface, and the second terminal is closer to the second surface than to the first surface.

A package structure includes a redistribution structure, a first conductive portion, a second conductive portion and a third conductive portion. The redistribution structure includes a first conductive pad and a second conductive pad. The first conductive portion is electrically connected with the first conductive pad. The second conductive portion is electrically connected with the second conductive pad. The first conductive portion at least partially overlaps the second conductive portion. The third conductive portion and the second conductive portion are located at the same layer. The third conductive portion does not overlap any conductive portion which is located at the same layer as the first conductive portion.

A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

An electronic power device including: a first electronic power component in which all the electrodes are arranged at a first main face of the first electronic power component; and an electric contact element in which a first main face is arranged against the first main face of the first electronic power component and which includes plural separate electrically conductive portions to which the electrodes of the first electronic power component are electrically connected. The first electronic power component and the electric contact element together form a stack such that a first lateral face of each of the portions of the electric contact element, substantially perpendicular to the first main face of the electric contact element, is arranged against at least one metallization of a support forming an electric contact of the first electronic power component.

Some embodiments include apparatus and methods using a package substrate and a die coupled to the package substrate. The package substrate includes conductive contacts, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate. The die includes buffer circuits and a calibration module coupled to the buffer circuits and the resistor. The buffer circuits include output nodes coupled to the conductive contacts through the conductive paths. The calibration module is configured to perform a calibration operation to adjust resistances of the buffer circuits based on a value of a voltage at a terminal of the resistor during the calibration operation.

A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers with cavities formed into the top and/or bottom. The cavities may then be used as locations for the electronic components. Alternatively, narrow spacer interposers may be used to space apart standard more laterally elongated interposers to form the indentations used to house the electronic components. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products.