Patent classifications
H01L2924/201
Circuit substrate
A circuit substrate includes a substrate, a wire build-up layer structure, and an insulating layer. The substrate has a first surface and a second surface opposites to the first surface. The substrate includes a plurality of patterned pads. The patterned pads are disposed on the first surface of the substrate, and having contact openings. The wire build-up layer structure is disposed on the first surface of the substrate. The wire build-up layer structure includes an interconnect build-up layer and a plurality of conductive pillars. The conductive pillars electrically connect to the interconnect build-up layer and the patterned pads. The insulating layer is disposed between the substrate and the wire build-up layer structure.
Bump bonded cryogenic chip carrier
A device has a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region; a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; and a superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius.
Bump bonded cryogenic chip carrier
A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius.
CIRCUIT SUBSTRATE
A circuit substrate includes a substrate, a wire build-up layer structure, and an insulating layer. The substrate has a first surface and a second surface opposites to the first surface. The substrate includes a plurality of patterned pads. The patterned pads are disposed on the first surface of the substrate, and having contact openings. The wire build-up layer structure is disposed on the first surface of the substrate. The wire build-up layer structure includes an interconnect build-up layer and a plurality of conductive pillars. The conductive pillars electrically connect to the interconnect build-up layer and the patterned pads. The insulating layer is disposed between the substrate and the wire build-up layer structure.
BUMP BONDED CRYOGENIC CHIP CARRIER
A device has a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region; a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; and a superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius.
BUMP BONDED CRYOGENIC CHIP CARRIER
A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius.
Electronic device interconnections for high temperature operability
Systems and methods are disclosed for providing an interconnection for extending high-temperature use in sensors and other electronic devices. The interconnection includes a semiconductor layer; an ohmic contact layer disposed on a first region of the semiconductor layer; an insulating layer disposed on a second region of the semiconductor layer, where the second region differs from the first region; a metal layer disposed above at least the insulating layer and the ohmic contact layer; and a connecting conductive region disposed on the metal layer and in vertical alignment with a third region of the semiconductor layer. The third region differs from the first region and is offset from the ohmic contact layer at the first region. The offset is configured to extend an operational lifetime of the interconnection apparatus, particularly when the interconnection apparatus is exposed to high temperature environments.
ELECTRONIC DEVICE INTERCONNECTIONS FOR HIGH TEMPERATURE OPERABILITY
Systems and methods are disclosed for providing an interconnection for extending high-temperature use in sensors and other electronic devices. The interconnection includes a semiconductor layer; an ohmic contact layer disposed on a first region of the semiconductor layer; an insulating layer disposed on a second region of the semiconductor layer, where the second region differs from the first region; a metal layer disposed above at least the insulating layer and the ohmic contact layer; and a connecting conductive region disposed on the metal layer and in vertical alignment with a third region of the semiconductor layer. The third region differs from the first region and is offset from the ohmic contact layer at the first region. The offset is configured to extend an operational lifetime of the interconnection apparatus, particularly when the interconnection apparatus is exposed to high temperature environments.
Method of bonding with silver paste
A method for bonding with a silver paste includes coating a semiconductor device or a substrate with the silver paste. The silver paste contains a plurality of silver particles and a plurality of bismuth particles. The method further includes disposing the semiconductor on the substrate and forming a bonding layer by heating the silver paste, wherein the semiconductor and the substrate are bonded to each other by the bonding layer.
Electronic device interconnections for high temperature operability
Systems and methods are disclosed for providing an interconnection for extending high-temperature use in sensors and other electronic devices. The interconnection includes a semiconductor layer; an ohmic contact layer disposed on a first region of the semiconductor layer; an insulating layer disposed on a second region of the semiconductor layer, where the second region differs from the first region; a metal layer disposed above at least the insulating layer and the ohmic contact layer; and a connecting conductive region disposed on the metal layer and in vertical alignment with a third region of the semiconductor layer. The third region differs from the first region and is offset from the ohmic contact layer at the first region. The offset is configured to extend an operational lifetime of the interconnection apparatus, particularly when the interconnection apparatus is exposed to high temperature environments.