Patent classifications
H01L2924/20108
METHOD FOR FABRICATING HYBRID BONDED STRUCTURE
A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.
BONDING WIRE FOR SEMICONDUCTOR DEVICE
The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.
BONDING WIRE FOR SEMICONDUCTOR DEVICE
The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.
Semiconductor device packages
A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.
3DIC Formation with Dies Bonded to Formed RDLs
A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.
Method of fabricating high-power module
A method is provided to fabricate a high-power module. A non-touching needle is used to paste a slurry on a heat-dissipation substrate. The slurry comprises nano-silver particles and micron silver particles. The ratio of the two silver particles is 9:1˜1:1. The slurry is pasted on the substrate to be heated up to a temperature kept holding. An integrated chip (IC) is put above the substrate to form a combined piece. A hot presser processes thermocompression to the combined piece to form a thermal-interface-material (TIM) layer with the IC and the substrate. After heat treatment, the TIM contains more than 99 percent of pure silver with only a small amount of organic matter. No volatile organic compounds would be generated after a long term of use. No intermetallic compounds would be generated while the stability under high temperature is obtained. Consequently, embrittlement owing to procedure temperature is dismissed.
Conductive paste and die bonding method
Provided are: a conductive paste in which sinterability of silver particles the conductive paste can be easily controlled by using silver particles having predetermined crystal transformation characteristics defined by an XRD analysis, and after a sintering treatment, excellent electrical conductivity and thermal conductivity can be stably obtained; and a die bonding method using the conductive paste. Disclosed is a conductive paste which includes silver particles having a volume average particle size of 0.1 to 30 μm as a sinterable conductive material, and a dispersing medium for making a paste-like form, and in which when the integrated intensity of the peak at 2θ=38°±0.2° in the X-ray diffraction chart obtainable by an XRD analysis before a sintering treatment of the silver particles is designated as S1, and the integrated intensity of the peak at 2θ=38°±0.2° in the X-ray diffraction chart obtainable by an XRD analysis after a sintering treatment (250° C., 60 minutes) of the silver particles is designated as S2, the value of S2/S1 is adjusted to a value within the range of 0.2 to 0.8.
BONDING WIRE FOR SEMICONDUCTOR DEVICE
There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices.
The bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, and the bonding wire contains In of 0.011 to 1.2% by mass and has the Pd coating layer of a thickness of 0.015 to 0.150 μm. With this configuration, it is able to increase the bonding longevity of a ball bonded part in a high-temperature and high-humidity environment, and thus to improve the bonding reliability. When the Cu alloy core material contains one or more elements of Pt, Pd, Rh and Ni in an amount, for each element, of 0.05 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 175° C. or more. When an Au skin layer is further formed on a surface of the Pd coating layer, wedge bondability improves.
BONDING WIRE FOR SEMICONDUCTOR DEVICE
There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices.
The bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, and the bonding wire contains In of 0.011 to 1.2% by mass and has the Pd coating layer of a thickness of 0.015 to 0.150 μm. With this configuration, it is able to increase the bonding longevity of a ball bonded part in a high-temperature and high-humidity environment, and thus to improve the bonding reliability. When the Cu alloy core material contains one or more elements of Pt, Pd, Rh and Ni in an amount, for each element, of 0.05 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 175° C. or more. When an Au skin layer is further formed on a surface of the Pd coating layer, wedge bondability improves.
Bonding wire for semiconductor devices
Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer.