A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

Provided are: a conductive paste in which sinterability of silver particles the conductive paste can be easily controlled by using silver particles having predetermined crystal transformation characteristics defined by an XRD analysis, and after a sintering treatment, excellent electrical conductivity and thermal conductivity can be stably obtained; and a die bonding method using the conductive paste. Disclosed is a conductive paste which includes silver particles having a volume average particle size of 0.1 to 30 μm as a sinterable conductive material, and a dispersing medium for making a paste-like form, and in which when the integrated intensity of the peak at 2θ=38°±0.2° in the X-ray diffraction chart obtainable by an XRD analysis before a sintering treatment of the silver particles is designated as S1, and the integrated intensity of the peak at 2θ=38°±0.2° in the X-ray diffraction chart obtainable by an XRD analysis after a sintering treatment (250° C., 60 minutes) of the silver particles is designated as S2, the value of S2/S1 is adjusted to a value within the range of 0.2 to 0.8.

There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices.

The bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, and the bonding wire contains In of 0.011 to 1.2% by mass and has the Pd coating layer of a thickness of 0.015 to 0.150 μm. With this configuration, it is able to increase the bonding longevity of a ball bonded part in a high-temperature and high-humidity environment, and thus to improve the bonding reliability. When the Cu alloy core material contains one or more elements of Pt, Pd, Rh and Ni in an amount, for each element, of 0.05 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 175° C. or more. When an Au skin layer is further formed on a surface of the Pd coating layer, wedge bondability improves.

There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices.

The bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, and the bonding wire contains In of 0.011 to 1.2% by mass and has the Pd coating layer of a thickness of 0.015 to 0.150 μm. With this configuration, it is able to increase the bonding longevity of a ball bonded part in a high-temperature and high-humidity environment, and thus to improve the bonding reliability. When the Cu alloy core material contains one or more elements of Pt, Pd, Rh and Ni in an amount, for each element, of 0.05 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 175° C. or more. When an Au skin layer is further formed on a surface of the Pd coating layer, wedge bondability improves.

Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer.