The present disclosure relates to a composition that includes a III-V planar substrate having a surface aligned with and parallel to a reference plane, where the surface includes a plurality of terraces, each terrace includes a first surface positioned between a first boundary and a second boundary, each boundary is substantially parallel to the other boundaries and positioned substantially parallel to the reference plane, and each terrace is separated from an adjacent terrace by a second surface positioned between the second boundary of the terrace and the first boundary of the adjacent terrace.

Provided is a semiconductor package structure including a first die having a first bonding structure thereon, a second die having a second bonding structure thereon, a metal circuit structure, and a first protective structure. The second die is bonded to the first die such that a first bonding dielectric layer of the first bonding structure contacts a second bonding dielectric layer of the second bonding structure. The metal circuit structure is disposed over a top surface of the second die. The first protective structure is disposed within the top surface of the second die, and sandwiched between the metal circuit structure and the second die.

In a graphene photodetector, in which a graphene film is electrically connected a first electrode and to a second electrode, the first electrode and the second electrode are formed of the same conductive material, and the first electrode and the second electrode have an asymmetric structure in interface regions with the graphene film.

Tunnel junctions for multijunction solar cells are provided. According to an aspect of the invention, a tunnel junction includes a first layer including p-type AlGaAs, a second layer including n-type GaAs, wherein the second layer is a quantum well, and a third layer including n-type AlGaAs or n-type lattice matched AlGaInP. The quantum well can be GaAs or AlxGaAs with x being more than about 40%, and lattice matched GaInAsNSb in the Eg range of from about 0.8 to about 1.4 eV.

Tunnel junctions for multijunction solar cells are provided. According to an aspect of the invention, a tunnel junction includes a first layer including p-type AlGaAs, a second layer including n-type GaAs, wherein the second layer is a quantum well, and a third layer including n-type AlGaAs or n-type lattice matched AlGaInP. The quantum well can be GaAs or AlxGaAs with x being more than about 40%, and lattice matched GaInAsNSb in the Eg range of from about 0.8 to about 1.4 eV.

The present disclosure relates to a micro light emitting diode (LED) display device including a substrate having a plurality of thin film transistors thereon; a plurality of micro light emitting devices (LEDs) on an upper surface of the substrate, the micro LEDs each having a protecting film provided with a first contact hole to expose a portion of an upper surface of a corresponding micro LED; at least one insulating layer covering the micro LED, the insulating layer provided with a second contact hole to expose a portion of the upper surface of the corresponding micro LED; and a connection electrode in the first contact hole and the second contact hole configured to transfer signals to the micro LED, wherein the first contact hole is larger than the second contact hole.

An ingot having a first surface, a second surface opposite to the first surface, and a third surface extending in a first direction from the second surface to the first surface and connecting the first and second surfaces includes a first mono-like crystalline portion, a first intermediate portion including one or more mono-like crystalline sections, and a second mono-like crystalline portion sequentially adjacent to one another in a second direction perpendicular to the first direction. The first and second mono-like crystalline portions have a greater width than the first intermediate portion in the second direction. A first boundary between the first mono-like crystalline portion and the first intermediate portion and a second boundary between the second mono-like crystalline portion and the first intermediate portion each include a coincidence boundary. At least one of the first or second boundary is curved in an imaginary cross section perpendicular to the first direction.

A semiconductor material having the molecular formula Cu2l2Se6 is provided. Also provided are solid solutions of semiconductor materials having the formulas Cu2lxBr2-xSeyTe6-y and Cu2lxBr2-xSeyS6-y, where 0≤x≤1 and 0≤y≤3. Methods and devices that use the semiconductor materials to convert incident radiation into an electric signal are also provided. The devices include optoelectronic and photonic devices, such as photodetectors, photodiodes, and photovoltaic cells.

Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.

Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.