Disclosed is a method of facilitating straining of a semiconductor element (331) for semiconductor fabrication. In a described embodiment, the method comprises: providing a base layer (320) with the semiconductor element (331) arranged on a first base portion (321) of the base layer (320), the semiconductor element (331) being subjected to a strain relating to a characteristic of the first base portion (321); and adjusting the characteristic of the first base portion (321) to facilitate straining of the semiconductor element (331).

A method of manufacturing an electronic component including a substrate is provided. The method includes generating a plasma remote from a sputter target, generating sputtered material from the sputter target using the plasma, and depositing the sputtered material on a substrate as a crystalline layer.

A method forms a part of a power semiconductor device. The method includes homoepitaxially forming two silicon carbide layers on a first side of a silicon carbide substrate and forming a pattern of pits on a second side of the silicon carbide substrate. The two layers include a buffer layer, on the first side of the silicon carbide substrate, and have a same doping type of the silicon carbide substrate and a doping concentration equal to or greater than 10.sup.17 cm.sup.−3 in order to increase the quality of at least one subsequent SiC layer. The two layers include an etch stopper layer, being deposited on the buffer layer and has a same doping type as the buffer layer but a lower doping concentration in order to block a trenching process. The pattern of pits, obtained by electrochemical etching, extends completely thorough the silicon carbide substrate and the buffer layer.

A display substrate, a display apparatus, and a manufacturing method for the display substrate are provided. The display substrate includes: a substrate and a plurality of pixel units arranged in an array on the substrate; the pixel unit includes a light emitting diode, a connecting metal pattern, and a thin film transistor arranged in sequence along a direction away from the substrate; the connecting metal pattern is conductively connected to a top electrode of the light emitting diode; an active layer of the thin film transistor is insulated and spaced from the connecting metal pattern, and the drain of the thin film transistor is conductively connected to the connecting metal pattern.

The present disclosure falls into the field of optoelectronics, particularly, includes the design, epitaxial growth, fabrication, and characterization of Laser Diodes (LDs) operating in the ultraviolet (UV) to infrared (IR) spectral regime on patterned substrates (PSs) made with (formed on) low cost, large size Si, or GaN on sapphire, GaN, and other wafers. We disclose three types of PSs, which can be universal substrates, allowing any materials (III-Vs, II-VIs, etc.) grown on top of it with low defect and/or dislocation density.

A pixel unit includes a substrate, a wiring layer and three light-emitting elements. The wiring layer includes first electrode wires and second electrode wires. The first electrode wires and the second electrode wires are arranged side by side and separated from each other by a spacing. A first blocking wall structure is at a first end portion of each of the first electrode wires, the first end portion is near the corresponding second electrode wires, and a second blocking wall structure is at a second end portion of each of the second electrode wires, the second end portion is near the corresponding first electrode wires. Three light-emitting elements emit red light, green light and blue light respectively. The light-emitting elements are in a flip chip configuration and are connected to one of the first electrode wires and one of the second electrode wires adjacent to each other respectively.

The present disclosure relates to a part including silicon carbide layer and manufacturing method thereof, and the manufacturing method according to the present disclosure includes preparing a graphite substrate, and laminating a silicon carbide layer on a surface of the graphite substrate, wherein at the laminating the silicon carbide layer, the silicon carbide layer is laminated such that the thickness of the silicon carbide layer is 0.01 to 1 times the thickness of the graphite substrate, thereby improving the durability of the part including silicon carbide layer.

Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may include a nitrogen-containing nucleation layer deposited on the substrate. The methods may include forming a silicon-containing material on at least a first portion of the nitrogen-containing nucleation layer. The methods may include forming a second layer of material on at least a second portion of the nitrogen-containing nucleation layer. The methods may include forming a masking layer on a portion of the second layer of material. The masking layer may cover less than or about 90% of the second layer of material. The methods may include growing the second layer of material through the masking layer. The methods may include coalescing the second layer of material above the masking layer.

A method for producing a multiplicity of semiconductor chips (13) is provided, comprising the following steps: providing a wafer (1) comprising a multiplicity of semiconductor bodies (2), wherein separating lines (9) are arranged between the semiconductor bodies (2), depositing a contact layer (10) on the wafer (1), wherein the material of the contact layer (10) is chosen from the following group: platinum, rhodium, palladium, gold, and the contact layer (10) has a thickness of between 8 nanometres and 250 nanometres, inclusive, applying; the wafer (1) to a film (11), at least partially severing the wafer (1) in the vertical direction along the separating lines (9) or introducing fracture nuclei (12) into the wafer (1) along the separating lines (9), and breaking the wafer (1) along the separating lines (9) or expanding the film (11) such that a spatial separation of the semiconductor chips (13) takes place, wherein the contact layer (10) is also separated. A semiconductor chip, a component and a method for producing the latter are also provided.

The present invention generally relates to nanoscale wires and, in particular, to nanoscale wires with heterojunctions, such as tip-localized homo- or heterojunctions. In one aspect, the nanoscale wire may include a core, an inner shell surrounding the core, and an outer shell surrounding the inner shell. The outer shell may also contact the core, e.g., at an end portion of the nanoscale wire. In some cases, such nanoscale wires may be used as electrical devices. For example a p-n junction may be created where the inner shell is electrically insulating, and the core and the outer shell are p-doped and n-doped. Other aspects of the present invention generally relate to methods of making or using such nanoscale wires, devices, or kits including such nanoscale wires, or the like.