A radiation emitting semiconductor chip may include a first semiconductor layer sequence, a second semiconductor layer sequence arranged on the first semiconductor layer sequence, a first contact structure configured to inject charge carriers into the first semiconductor layer sequence, and a contact layer sequence configured to inject charge carriers into the second semiconductor layer sequence. The first contact structure and the contact layer sequence may be formed without overlapping in lateral directions in plan view. The contact layer sequence may have a sheet resistance, which increases in the direction of the first contact structure.

A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.

A display device including a wiring area including a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction crossing the first direction, a transmissive area surrounded by the wiring area and configured to transmit light, a plurality of pixel drivers respectively connected to one of the plurality scan lines and one of the plurality of data lines, a first pad electrode and a second pad electrode overlapping a first pixel driver from among the plurality of pixel drivers, a light emitting element on the first pad electrode and the second pad electrode, a first supplement electrode overlapping the first pad electrode, and a second supplement electrode overlapping the second pad electrode.

This application provides semiconductor structures and methods of manufacturing the same. A semiconductor structure includes: an N-type semiconductor layer, a light emitting layer, and a P-type ion doped layer that are disposed from bottom to up, wherein the P-type ion doped layer comprises an activated region and non-activated regions located on two sides of the activated region, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated region are passivated. The layout of the activated region and the non-activated regions makes an LED include: a high-efficiency light emitting region and light emitting obstacle regions located on two sides of the high-efficiency light emitting region.

Described are light emitting diode (LED) devices comprising a plurality of mesas defining pixels, each of the mesas comprising semiconductor layers, an N-contact material in a space between each of the plurality of mesas, a dielectric material which insulates sidewalls of the P-type layer and the active region from the metal. A hard mask layer is above the semiconductor layers, the hard mask layer having a plurality of openings therein, each partially filled with a liner layer and partially filled with a P-metal material plug, the P-metal material plug having a width; and a passivation film is on the hard mask layer, the passivation film having a plurality of passivation film openings therein defining a width, the width of each passivation film opening being less than the width of a combination of the P-metal material plug and the liner layer.

A light-emitting diode includes a light-emitting structure, a first insulating layer and a first electrode layer. The first electrode layer is formed on the first insulating layer and in the first opening, and is electrically connected to the first semiconductor layer through the first opening. The first electrode layer includes a first metal reflective layer and a stress adjustment layer. The first metal reflective layer in the first opening is in contact with the first semiconductor layer, and located between the first semiconductor layer and the stress adjustment layer. The first metal reflective layer and the stress adjustment layer contain a same metal element, and a content of the same metal element in the first metal reflective layer is greater than that in the stress adjustment layer.

In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence including a first semiconductor layer, a second semiconductor layer, and an active layer arranged between the first semiconductor layer and the second semiconductor layer, a via having a plurality of recesses and a contact layer, wherein the first semiconductor layer has a first electrical contact region, wherein the second semiconductor layer has a second electrical contact region, wherein the via completely penetrates the first semiconductor layer and the active layer and is electrically connected to the second contact region, wherein the first contact region is arranged within the recesses of the via, and wherein the first contact region is divided into a plurality of partial regions, each partial region being arranged in one of the recesses and the partial regions being separated from each other.

A deep ultraviolet light emitting device includes: an electron block layer of a p-type AlGaN-based semiconductor material or a p-type AlN-based semiconductor material provided on a support substrate; an active layer of an AlGaN-based semiconductor material provided on the electron block layer; an n-type clad layer of an n-type AlGaN-based semiconductor material provided on the active layer; an n-type contact layer provided on a partial region of the n-type clad layer and made of an n-type semiconductor material containing gallium nitride (GaN); and an n-side electrode formed on the n-type contact layer. The n-type contact layer has a band gap smaller than that of the n-type clad layer.

In an embodiment a radiation-emitting semiconductor chip includes a semiconductor body having an active region configured to generate radiation, a first contact layer having a first contact area and a first contact finger structure connected to the first contact area, a second contact layer having a second contact area and a second contact finger structure connected to the second contact area, a current distribution layer electrically conductively connected to the first contact layer, a connection layer electrically conductively connected to the first contact layer via the current distribution layer and an insulation layer, wherein the insulation layer is arranged in places between the connection layer and the current distribution layer, wherein the insulation layer has at a plurality of openings, in which the connection layer and the current distribution layer adjoin one another, and wherein edge regions of the insulation layer includes more openings than a central region of the insulation layer.

A semiconductor component may include a first compressive strain layer on top of a semiconductor body. A material for the first compressive strain layer may include Ta, Mo, Nb, compounds thereof, and combinations thereof.