A coated conductor comprises a substrate supporting a ReBCO superconductor adapted to carry current in a superconducting state. The superconductor is characterized in having peaks in critical current (J.sub.c) of at least 0.2 MA/cm.sup.2 in a magnetic field of about 1 Tesla when the field is applied normal to the surface of the superconductor and when the field is applied parallel to the surface of the superconductor, and further characterized in that the superconductor includes horizontal defects and columnar detects in a size and an amount sufficient to result in the said critical current response. The conductor is characterized in that the ratio of the height of the peaks in the J.sub.c is in the range from 3:1 with the ratio of the field perpendicular (0 degrees) to the field parallel (+/−90 degrees) to the range from 3:1 with the ratio of the field parallel to the field perpendicular.

A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.

This disclosure teaches methods for making high-temperature superconducting striated tape combinations and the product high-temperature superconducting striated tape combinations. This disclosure describes an efficient and scalable method for aligning and bonding two superimposed high-temperature superconducting (HTS) filamentary tapes to form a single integrated tape structure. This invention aligns a bottom and top HTS tape with a thin intervening insulator layer with microscopic precision, and electrically connects the two sets of tape filaments with each other. The insulating layer also reinforces adhesion of the top and bottom tapes, mitigating mechanical stress at the electrical connections. The ability of this method to precisely align separate tapes to form a single tape structure makes it compatible with a reel-to-reel production process.

The present disclosure provides a two-dimensional scalable superconducting qubit structure and a method for controlling a cavity mode thereof. The two-dimensional scalable superconducting qubit structure includes: a superconducting qubit chip comprising a plurality of two-dimensionally distributed and scalable qubits; a capacitor part of each of the qubits has at least five arms distributed two-dimensionally, two of the at least five arms in each qubit are respectively connected with a read coupling circuit and a control circuit, and the other at least three arms are coupled with adjacent qubits through a coupling cavity.

A device includes a first substrate having a principal surface; a second substrate having a principal surface, in which the first substrate is bump-bonded to the second substrate such that the principal surface of the first substrate faces the principal surface of the second substrate; a circuit element having a microwave frequency resonance mode, in which a first portion of the circuit element is arranged on the principal surface of the first substrate and a second portion of the circuit element is arranged on the principal surface of the second substrate; and a first bump bond connected to the first portion of the circuit element and to the second portion of the circuit element, in which the first superconductor bump bond provides an electrical connection between the first portion and the second portion.

A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

A superconductor magnetic field effect transistor. The superconductor magnetic field effect transistor may include a sheet of a superconducting material; and a solenoid. The sheet may be substantially flat, and the solenoid may include a plurality of turns, each of the turns being substantially parallel to the sheet. The superconducting material may be a type-II superconducting material.

Methods, devices, and systems are described for forming a superconducting qubit. An example device may comprise a substrate having a first surface and a patterned layer adjacent the substrate and comprising tantalum in an alpha phase. The patterned layer may comprise at least a part of a structure for storing a quantum state.

There is described herein a method for fabricating a tunnel junction. The method comprises coating a substrate with an inorganic resist layer and forming support pillars in the resist layer; fabricating a mask on the resist layer from a first inorganic material, the mask having at least one opening; removing the resist layer from beneath the mask, leaving behind the support pillars supporting the mask above the substrate; performing shadow evaporation on the substrate through the at least one opening of the mask to form the tunnel junction on the substrate; and removing the mask and the support pillars from the substrate.