H01P3/003

Superconducting bilayers of two-dimensional materials with integrated Josephson junctions

Josephson junctions (JJ) based on bilayers of azimuthally misaligned two-dimensional materials having superconducting states are provided. Also provided are electronic devices and circuits incorporating the JJs as active components and methods of using the electronic devices and circuits. The JJs are formed from bilayers composed of azimuthally misaligned two-dimensional materials having a first superconducting segment and a second superconducting segment separated by a weak-link region that is integrated into the bilayer.

Distributed Circuit
20230006625 · 2023-01-05 ·

A distributed amplifier includes a transmission line configured so as to transmit a signal, a variable capacitor having one end connected to the transmission line and the other end connected to the ground, and configured so that the capacitance is adjustable, and a variable capacitor having one end connected to the transmission line and the other end connected to the ground, and configured so that the capacitance is adjustable. The transmission line is configured in such a manner that the inductance is adjustable.

Reduced Kapitza resistance microwave filter for cryogenic environments

An architecture for, and techniques for fabricating, a thermal decoupling device are provided. In some embodiments, thermal decoupling device can be included in a thermally decoupled cryogenic microwave filter. In some embodiments, the thermal decoupling device can comprise a dielectric material and a conductive line. The dielectric material can comprise a first channel that is separated from a second channel by a wall of the dielectric material. The conductive line can comprise a first segment and a second segment that are separated by the wall. The wall can facilitate propagation of a microwave signal between the first segment and the second segment and can reduce heat flow between the first segment and the second segment of the conductive line.

SEMICONDUCTOR DEVICE

A 2nd signal line has impedance lower than impedance of a 1st signal line. A capacitor includes a 1st extension part and a 2nd extension part, a 1st ground part and a 2nd ground part. The 1st extension part and the 2nd extension part are connected to a 2nd signal line and are provided on an insulation substrate to extend along a longitudinal direction of the 2nd signal line. The 1st ground part and the 2nd ground part are at least a part of a ground pattern, and are provided between the 1st extension part and the 2nd extension part and the 2nd signal line, and between the 1st extension part and the 2nd extension part and an end part of the insulation substrate, to be electrically coupled with the 1st extension part and the 2nd extension part.

SIGNAL AND GROUND VIAS IN A GLASS CORE TO CONTROL IMPEDANCE

Embodiments described herein may be related to apparatuses, processes, and techniques related to positioning signal and ground vias, or ground planes, in a glass core to control impedance within a package. Laser-assisted etching processes may be used to create vertical controlled impedance lines to enhance bandwidth and bandwidth density of high-speed signals on a package. Other embodiments may be described and/or claimed.

COMPACT SURFACE TRANSMISSION LINE WAVEGUIDES WITH VERTICAL GROUND PLANES

Embodiments disclosed herein include coplanar waveguides and methods of forming coplanar waveguides. In an embodiment, a coplanar waveguide comprises a core, and a signal trace on the core. In an embodiment, the signal trace has a first edge and a second edge. In an embodiment, a first ground trace is over the core, and the first ground trace is adjacent to the first edge of the signal trace. In an embodiment, a first ground via plane is below the first ground trace. The coplanar waveguide may further comprise a second ground trace over the core, and the second ground trace is adjacent to the second edge of the signal trace. In an embodiment, a second ground via plane below the second ground trace.

Low footprint resonator in flip chip geometry
11527696 · 2022-12-13 · ·

A device includes a first substrate having a principal surface; a second substrate having a principal surface, in which the first substrate is bump-bonded to the second substrate such that the principal surface of the first substrate faces the principal surface of the second substrate; a circuit element having a microwave frequency resonance mode, in which a first portion of the circuit element is arranged on the principal surface of the first substrate and a second portion of the circuit element is arranged on the principal surface of the second substrate; and a first bump bond connected to the first portion of the circuit element and to the second portion of the circuit element, in which the first superconductor bump bond provides an electrical connection between the first portion and the second portion.

NANOWIRE-BASED INTEGRATED VIA IN ANODIC ALUMINUM OXIDE LAYER FOR CMOS APPLICATIONS

A complementary metal-oxide-semiconductor (CMOS) device includes a metal oxide layer comprising anodic aluminum oxide (AAO) and one or more nanowires (NW) of an electrically conducting material each formed within a corresponding pore extending through the AAO from a first side of the layer to a second side of the layer opposite the first side, a first electrically conducting layer disposed on the first side of the metal oxide layer, and a second electrically conducting layer disposed on the second side of the metal oxide layer. The nanowires form a via electrically connecting first electrically conducting layer and the second electrically conducting layer.

ADHESION LAYER FOR FORMING NANOWIRES IN ANODIC ALUMINUM OXIDE LAYER

A method for forming anodic aluminum oxide (AAO) on a substrate includes disposing an Al layer on the substrate, there being a Cu layer between the substrate and the Al layer, and a TiW alloy layer between and in contact with the Cu layer and the Al layer, anodizing the Al layer to provide an AAO layer comprising nanopores extending into the AAO layer to a barrier layer of the AAO at a base of each nanopore and converting at least some of the TiW alloy layer to TiW oxide, over-anodizing the barrier layer to remove at least a portion of the AAO of the barrier layer at the base of each nanopore, and exposing the AAO layer, the TiW oxide, and the TiW to a chemical etchant sufficient to extend the nanopores through the AAO layer to a surface of the Cu layer.

Transition in a multi-layer substrate between a substrate integrated waveguide portion and a coplanar waveguide portion

Transitional elements to offset a capacitive impedance in a transmission line are disclosed. Described are various examples of transitional elements in a multilayer substrate that introduce a transitional reactance to cancel the transmission line capacitive effects. The transitional elements reduce insertion loss.