H01S5/2223

Manufacturing Method for Semiconductor Device
20230021415 · 2023-01-26 ·

A first burying layer burying a side of a first ridge structure is formed by selective growth using a first selective growth mask and a third selective growth mask. The first burying layer is formed by regrowth from a surface of a second semiconductor layer on a side of the first ridge structure. At the same time, by selective growth using a second selective growth mask and a fourth selective growth mask, a second burying layer burying a side of a second ridge structure is formed. The second burying layer is formed by regrowth from a surface of a fourth semiconductor layer on a side of the second ridge structure.

TUNABLE WAVELENGTH GAIN CHIP ARRAY FOR SENSING AND COMMUNICATION
20230198218 · 2023-06-22 ·

An array of surface-emitting gain chips includes a common substrate, plural gain chips formed on the common substrate, each configured to generate a light beam, plural optical couplers, each located on a top surface of a corresponding gain chip of the plural gain chips, plural optical fibers, each connected with one end to a corresponding optical coupler of the plurality of optical couplers, an array wide optical coupler connected to another end of the plural optical fibers, and a single optical fiber connected to the array wide optical coupler and configured to output the combined light beams.

O-BAND SILICON-BASED HIGH-SPEED SEMICONDUCTOR LASER DIODE FOR OPTICAL COMMUNICATION AND ITS MANUFACTURING METHOD

The present invention proposes an O-band silicon-based high-speed semiconductor laser diode for optical communication and its manufacturing method, by using different buffer layers to form the growth surface of InP material with low dislocation density; N—InAlGaAs is used instead of conventional N—InAlAs electron-blocking layer in the epi-structure to reduce the barrier for electrons to enter the quantum wells from N-type and lower the threshold; a superlattice structure quantum barrier is used instead of a single layer barrier structure to improve the transport of heavy holes in the quantum wells; and the material structure is adjusted to achieve a reliable O-band high direct modulation speed semiconductor laser diode for optical communication on silicon substrate.

NARROW LINEWIDTH LASER WITH FLAT FREQUENCY MODULATION RESPONSE

A laser comprising a narrow linewidth, comprising: a grating along a laser cavity; a laser waveguide having a plurality of waveguide sections corresponding to a plurality of grating sections, each of the plurality of waveguide sections having a ridge/mesa width for detuning the grating in each of the plurality of grating sections; and a plurality of contact electrodes contacting each of the plurality of waveguide sections, the plurality of contact electrodes for applying a different current to each of the plurality of waveguide sections to enable active feedback noise suppression.

BURIED HETEROSTRUCTURE SEMICONDUCTOR LASER AND METHOD OF MANUFACTURE

A heterostructure laser is provided comprising an epitaxially grown substrate of first dopant type, an active region and layer of second dopant type, a narrow mesa having less than 20% open area and a side wall slope of less than 85 degrees, wherein said narrow mesa is etched through the active region and layer of second dopant type using in-situ MOCVD, a plurality of current blocking layers, an overclad layer and a contact layer of second dopant type, and an isolation mesa incorporating the narrow mesa, wherein the isolation mesa is etched through the active region, layer of second dopant type and plurality of current blocking layers and wherein the plurality of current blocking layers is grown without exposure to oxygen.

Buried-type semiconductor optical device

A buried semiconductor optical device comprises a semiconductor substrate; a mesa-stripe portion including a multi-quantum well layer on the semiconductor substrate; a buried layer consisting of a first portion and a second portion, the first portion covering one side of the mesa-stripe portion, the second portion covering the other side of the mesa-stripe portion, and the first portion and the second portion covering a surface of the semiconductor substrate; and an electrode configured to cause an electric current to flow through the mesa-stripe portion, the buried layer comprising, from the surface, a first, second, and third sublayer, the first and third sublayer each consisting of semi-insulating InP, the first sublayer and the second sublayer forming a pair structure, the second sublayer being located above the multi-quantum well layer, and the second sublayer consisting of one or more layers selected from InGaAs, InAlAs, InGaAlAs, InGaAsP, and InAlAsP.

SEMICONDUCTOR LASER, SEMICONDUCTOR LASER DEVICE, AND SEMICONDUCTOR LASER PRODUCTION METHOD

A semiconductor laser comprises a ridge formed on an n-type semiconductor substrate, a buried layer buried so as to cover both sides in an x-direction perpendicular to a y-direction, which is the direction in which the ridge extends. In a positive side of a z-direction that is the direction in which the ridge protrudes and the positive side of the buried layer in the z-direction, provided are a p-type second cladding layer, a p-type contact layer, a surface-side electrode that is connected to the p-type contact layer, and a semi-insulating layer that is formed on an outer edge separated from the ridge in the x-direction. The semi-insulating layer or the front surface-side electrode is formed on sides toward x-direction ends of the semiconductor laser on the positive side in the z-direction.

VERTICAL CAVITY SURFACE EMITTING DEVICE WITH A BURIED INDEX GUIDING CURRENT CONFINEMENT LAYER

A vertical cavity surface emitter device (e.g., VCSEL or RC-LED) containing a buried index-guiding current confinement aperture layer which is grown, and lithographically processed to define position, shape and dimension of an inner aperture. In a regrowth process, the aperture is filled with a single crystalline material from the third contact layer. The aperture provides for both current and optical confinement, while allowing for higher optical power output and improved thermal conductivity.

BURIED-TYPE SEMICONDUCTOR OPTICAL DEVICE

A buried semiconductor optical device comprises a semiconductor substrate; a mesa-stripe portion including a multi-quantum well layer on the semiconductor substrate; a buried layer consisting of a first portion and a second portion, the first portion covering one side of the mesa-stripe portion, the second portion covering the other side of the mesa-stripe portion, and the first portion and the second portion covering a surface of the semiconductor substrate; and an electrode configured to cause an electric current to flow through the mesa-stripe portion, the buried layer comprising, from the surface of the semiconductor substrate, a first sublayer, a second sublayer, and a third sublayer, the first sublayer, the second sublayer, and the third sublayer each consisting of semi-insulating InP, the first sublayer and the second sublayer forming a pair structure, the second sublayer being located above the multi-quantum well layer from the surface of the semiconductor substrate, and the second sublayer consisting of one or more layers selected from a group of InGaAs, InAAs, InGaAAs, InGaAsP, and InAlAsP.

III-V-ON-SILICON NANORIDGE OPTO-ELECTRONIC DEVICE WITH CARRIER BLOCKING LAYERS
20200203929 · 2020-06-25 ·

The disclosed technology relates to the development of a monolithic active electro-optical device. The electro-optical device may be fabricated using the so-called nanoridge aspect ratio trapping (ART) approach. In one aspect, the disclosed technology is directed to a monolithic integrated electro-optical device, which comprises a III-V-semiconductor-material ridge structure arranged on a Si-based support region. The ridge structure includes a first-conductivity-type bottom region arranged on the support region, a first-conductivity-type lower blocking layer arranged on the top surface and parts of the side surfaces of the bottom region and configured to block second-conductivity-type charge carriers, a not-intentionally-doped (NID) intermediate region arranged on the top and side surfaces of the lower blocking layer and containing a recombination region, a second-conductivity-type upper blocking layer arranged on the top and side surfaces of the intermediate region and configured to block first-conductivity-type charge carriers, and a second-conductivity-type top region arranged on the top and side surfaces of the upper blocking layer.