Electrical devices operating in a range of 273 C. to 100 C. are disclosed. The devices include an insulating substrate. A UO.sub.2+x crystal or oriented crystal UO.sub.2+x film is on a first portion of the substrate. The UO.sub.2+x crystal or film originates and hosts a non-equilibrium polaronic quantum phase-condensate. A first lead on a second portion of the substrate is in electrical contact with the UO.sub.2+x crystal or film. A second lead on a third portion of the surface is in electrical contact with the UO.sub.2+x crystal or film. The leads are isolated from each other. A UO.sub.2+x excitation source is in operable communication with the UO.sub.2+X crystal or film. The source is configured to polarize a region of the crystal or film thereby activating the non-equilibrium quantum phase-condensate. One source state causes the UO.sub.2+X crystal or film to be conducting. Another source state causes the UO.sub.2+x crystal or film to be non-conductive.

Electrical devices operating in a range of 273 C. to 100 C. are disclosed. The devices include an insulating substrate. A U0.sub.2+x crystal or oriented crystal U0.sub.2+x film is on a first portion of the substrate. The U0.sub.2+x crystal or film originates and hosts a non-equilibrium polaronic quantum phase-condensate. A first lead on a second portion of the substrate is in electrical contact with the U0.sub.2+x crystal or film. A second lead on a third portion of the surface is in electrical contact with the U0.sub.2+x crystal or film. The leads are isolated from each other. A U0.sub.2+x excitation source is in operable communication with the UO.sub.2+x crystal or film. The source is configured to polarize a region of the crystal or film thereby activating the non-equilibrium quantum phase-condensate. One source state causes the UO.sub.2+x crystal or film to be conducting. Another source state causes the U0.sub.2+x crystal or film to be non-conductive.

A semiconductor device includes an array of VCSEL devices with an annealed oxygen implant region (annealed at a temperature greater than 800 C.) that surrounds and extends laterally between the VCSEL devices. A common anode and a common cathode can be electrically coupled to the VCSEL devices, with the common anode overlying the annealed oxygen implant region. The annealed oxygen implant region can funnel current into active optical regions of the VCSEL devices and provide current isolation between the VCSEL devices while avoiding an isolation etch between VCSEL devices. In another embodiment, a semiconductor device includes an annealed oxygen implant region surrounding a VCSEL device. The VCSEL device(s) can be formed from a multi-junction layer structure where built-in hole charge Q.sub.p for an intermediate p-type layer relative to built-in electron charge Q.sub.n for a bottom n-type layer is configured for diode-like current-voltage characteristics of the VCSEL device(s).

A semiconductor device includes an array of VCSEL devices with an annealed oxygen implant region (annealed at a temperature greater than 800 C.) that surrounds and extends laterally between the VCSEL devices. A common anode and a common cathode can be electrically coupled to the VCSEL devices, with the common anode overlying the annealed oxygen implant region. The annealed oxygen implant region can funnel current into active optical regions of the VCSEL devices and provide current isolation between the VCSEL devices while avoiding an isolation etch between VCSEL devices. In another embodiment, a semiconductor device includes an annealed oxygen implant region surrounding a VCSEL device. The VCSEL device(s) can be formed from a multi-junction layer structure where built-in hole charge Q.sub.p for an intermediate p-type layer relative to built-in electron charge Q.sub.n for a bottom n-type layer is configured for diode-like current-voltage characteristics of the VCSEL device(s).