H01S5/3077

SEMICONDUCTOR LAYER STACK AND METHOD FOR PRODUCING SAME

A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap,

[00001] E F - E V < E G 2

applying to the layer (A) and

[00002] E L - E F < E G 2

applying to the layer (B), with E.sub.F the energy position of the Fermi level, E.sub.V the energy position of the valence band, E.sub.L the energy position of a conduction band and E.sub.L−E.sub.V the energy difference of the semiconductor band gap E.sub.G, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results.

SEMICONDUCTOR INTEGRATED CIRCUIT AND METHODOLOGY FOR MAKING SAME
20220059993 · 2022-02-24 ·

Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include at least one n-type layer, an inverted p-type modulation doped quantum well (mod-doped QW) structure, a non-inverted n-type mod-doped QW structure, and at least one p-type layer including a first P+-type layer formed below a second P-type layer. An etch operation exposes the second p-type layer. P-type ions are implanted into the exposed second p-type layer. A gate electrode of a n-channel HFET device is formed in contact with the p-type ion implanted region. Source and drain electrodes of the n-channel HFET device are formed in contact with n-type ion implanted regions formed in contact with the n-type mod-doped QW structure. P-channel HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.

Modulation doped semiconductor laser and manufacturing method therefor

A modulation doped semiconductor laser includes a multiple quantum well composed of a plurality of layers including a plurality of first layers and a plurality of second layers stacked alternately and including an acceptor and a donor; a p-type semiconductor layer in contact with an uppermost layer of the plurality of layers; and an n-type semiconductor layer in contact with a lowermost layer of the plurality of layers, the plurality of first layers including the acceptor so that a p-type carrier concentration is 10% or more and 150% or less of the p-type semiconductor layer, the plurality of second layers containing the acceptor so that the p-type carrier concentration is 10% or more and 150% or less of the p-type semiconductor layer, the plurality of second layers containing the donor, and an effective carrier concentration corresponding to a difference between the p-type carrier concentration and an n-type carrier concentration is 10% or less of the p-type carrier concentration of the plurality of second layers.

VERTICAL CAVITY SURFACE EMITTING LASER ELEMENT
20220029387 · 2022-01-27 · ·

A vertical cavity surface emitting laser element includes a first light reflecting film, a nitride semiconductor layered body, a p-electrode and a second light reflecting film. The nitride semiconductor layered body includes an n-side semiconductor layer disposed on the first light reflecting film, an active layer disposed on the n-side semiconductor layer, and a p-side semiconductor layer disposed on the active layer. The p-side semiconductor layer includes a protrusion and a surface around the protrusion. The p-electrode is in contact with an upper surface of the protrusion, and extends to the surface around the protrusion. The p-electrode is light-transmissive. The second light reflecting film is disposed on the p-electrode. A height of the protrusion as measured from the surface around the protrusion is smaller than a thickness of the p-electrode.

Surface-emitting laser device and light emitting device including the same

Surface-emitting laser devices and light-emitting devices including the same are provided. A surface-emitting laser device can include: a first reflective layer and a second reflective layer; and an active region disposed between the first reflective layer and the second reflective layer, wherein the first reflective layer includes a first group first reflective layer and a second group first reflective layer, and the second reflective layer includes a first group second reflective layer and a second group second reflective layer.

SiGeSn laser diodes and method of fabricating same

A laser diode including a double heterostructure comprising a top layer, a buffer layer formed on a substrate, and an intrinsic active layer formed between the top layer and the buffer layer. The top layer and the buffer layer have opposite types of conductivity. The active layer has a bandgap smaller than that of the buffer layer or the top layer. The double heterostructure includes Ge, SiGe, GeSn, and/or SiGeSn materials.

Semiconductor optical element, semiconductor optical element forming structure, and method of manufacturing semiconductor optical element using the same

A semiconductor optical element includes: a first conductivity type semiconductor substrate; and a laminated body disposed on the first conductivity type semiconductor substrate. The laminated body includes, in the following order from a side of the first conductivity type semiconductor substrate: a first conductivity type semiconductor layer; an active layer; a second conductivity type semiconductor layer; and a second conductivity type contact layer. The second conductivity type semiconductor layer includes: a carbon-doped semiconductor layer in which carbon is doped as a dopant in a compound semiconductor; and a group 2 element-doped semiconductor layer in which a group 2 element is doped as a dopant in a compound semiconductor. The carbon-doped semiconductor layer is disposed at a position closer to the active layer than the group 2 element-doped semiconductor layer.

SEMICONDUCTOR OPTICAL ELEMENT, SEMICONDUCTOR OPTICAL ELEMENT FORMING STRUCTURE, AND METHOD OF MANUFACTURING SEMICONDUCTOR OPTICAL ELEMENT USING THE SAME

A semiconductor optical element includes: a first conductivity type semiconductor substrate; and a laminated body disposed on the first conductivity type semiconductor substrate. The laminated body includes, in the following order from a side of the first conductivity type semiconductor substrate: a first conductivity type semiconductor layer; an active layer; a second conductivity type semiconductor layer; and a second conductivity type contact layer. The second conductivity type semiconductor layer includes: a carbon-doped semiconductor layer in which carbon is doped as a dopant in a compound semiconductor; and a group 2 element-doped semiconductor layer in which a group 2 element is doped as a dopant in a compound semiconductor. The carbon-doped semiconductor layer is disposed at a position closer to the active layer than the group 2 element-doped semiconductor layer.

Semiconductor layer stack and method for producing same

A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap, E F - E V < E G 2
applying to the layer (A) and E L - E F < E G 2
applying to the layer (B), with E.sub.F the energy position of the Fermi level, E.sub.V the energy position of the valence band, E.sub.L the energy position of a conduction band and E.sub.L−E.sub.V the energy difference of the semiconductor band gap E.sub.G, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results.

Manufacturing method of a group III-V compound semiconductor device
11417524 · 2022-08-16 · ·

A manufacturing method of a group III-V compound semiconductor device, the method includes: a first process in which a group V material gas and an impurity material gas are supplied to a reacting furnace which is set at a first temperature of a range from 400° C. to 500° C. and a first pressure of a range from 100 hPa to 700 hPa, and impurities are doped in an undoped group III-V compound semiconductor layer, and a second process in which the supply of the impurity material gas is stopped, a temperature of the reacting furnace is raised to a second temperature which is higher than the first temperature, a pressure of the reacting furnace is set lower than a pressure of the first pressure, a supply of an etching gas is initiated and the supply of the group V material gas is continued.