The present disclosure provides a motor drive device. The motor drive device includes a current detection unit, a control unit and a determination unit. The current detection unit detects a current flowing through a motor coil. The control unit executes a slow attenuation mode that attenuates the current after an end of a power supply mode. The determination unit determines whether the current at a second time point while a predetermined time has elapsed from a first time point when the power supply mode is switched to a slow decay mode is below a limit value. When the determination unit determines that the current does not fall below the limit value, the control unit is configured to switch from the slow attenuation mode to a fast attenuation mode at the second time point.

Methods and apparatuses for detecting an open load condition for a load. The load is coupled to a power source at a high side and to a ground at a low side through at least one switch, the load has a first end and a second end, a first voltage at the first end is kept constant. A switch is controlled by a PWM signal. After the switch is turned off by the PWM signal, the voltage associated with the second end of the load is measured. In one embodiment, a change of the second voltage during a predefined delay is compared with a predefined voltage threshold. In another embodiment, the time it takes for the change of the second voltage to reach a predefined voltage threshold is compared with a predefined time threshold.

The present disclosure provides an image device. The image device may include a camera lens, one or more stepper motors to drive the camera lens, one or more H-bridge circuits configured to control at least one of the one or more stepper motors, and a lens-identification circuit connected with the one or more H-bridge circuits, wherein the lens-identification circuit includes an impedance network of which an impedance value corresponds to a type of the camera lens.

A current limit protecting system and method of a motor pre-driver are provided. A current limiting circuit detects a current of a resistor that is connected to a motor, and then compares the current of the resistor with a current threshold to output a current comparing signal. When a controller circuit determines that the current of the resistor is larger than the current threshold according to the current comparing signal, and a working period of a first signal of a first node or a working period of a second signal of a second node of the motor reaches a preset value, a first high-side switch and a second high-side switch are turned off, and a first low-side switch and a second low-side switch are alternately turned on. As a result, a temperature of the motor generally reduces.

The present disclosure provides an image device. The image device may include a camera lens, one or more stepper motors to drive the camera lens, one or more H-bridge circuits configured to control at least one of the one or more stepper motors, and a lens-identification circuit connected with the one or more H-bridge circuits, wherein the lens-identification circuit includes an impedance network of which an impedance value corresponds to a type of the camera lens.

The present disclosure provides a motor drive circuit. The motor drive circuit includes a first-phase half bridge circuit and a second-phase half bridge circuit. The first and second phase half bridge circuits include first-phase and second-phase high-side FETs and first-phase and second-phase low-side FETs. The first-phase and second-phase high-side FETs are configured to apply a first voltage to a first end. A second end of the first-phase and second-phase high-side FETs is connected to the first end. A second voltage lower than the first voltage is applied to the second end. The first-phase low-side FET or the second-phase high-side FET is disposed between the first-phase high-side FET and the second-phase low-side FET. The second-phase low-side FET or the first-phase high-side FET is disposed between the first-phase low-side FET and the second-phase high-side FET.

An apparatus with load dump protection incorporates first and second half-bridge circuits, first and second comparators, and first and second clamping circuits. The first comparator compares a supply voltage with a first set voltage and generates a first comparison signal while the supply voltage exceeds the first set voltage. The second comparator compares the supply voltage with a second set voltage and generates a second comparison signal while the supply voltage exceeds the second set voltage. The first clamping circuit divides the supply voltage and provides a divided voltage to the first half-bridge circuit in response to the second comparison signal. The second clamping circuit divides the supply voltage and provides a divided voltage to the second half-bridge circuit in response to the second comparison signal.

An integrated circuit comprising: an input terminal configured to receive a failure-event-signal representative of a failure event; a first output terminal configured to provide a first-failure-signal; and a second output terminal configured to provide a second-failure-signal; and a processing block configured to: set the first-failure-signal based on the failure-event-signal; and set the second-failure-signal, at a predetermined time interval after the first-failure-signal is set. The processing block further comprises a switch configured selectively, based on a received digital-error-signal to either: set the second-failure-signal based on a digital-counter-output-signal; or set the second-failure-signal based on an analogue-trigger-signal.

A digital power supply protection circuit includes: a signal preprocessing circuit, configured to receive an overcurrent signal and a first inceptive impulse clock timing, and perform preprocessing on the overcurrent signal according to the first inceptive impulse clock timing so as to obtain a first reference signal a signal generation circuit, configured to receive the first inceptive impulse clock timing, count time duration between a rising edge of the first inceptive impulse clock timing and a rising edge of the first reference signal so as to obtain a first time duration, and upon the first time duration is greater than a second time duration, generate a first disabling signal by delaying the rising edge of the first inceptive impulse clock timing for the second time duration; and a clock timing adjustment circuit, configured to adjust the first inceptive impulse clock timing according to the first disabling signal.

A motor drive device includes a plurality of control systems that individually supply drive currents to a plurality of coil groups included in a motor. The motor drive device independently sets the current command values for the respective control systems. Based on the set current command values, drive instructions are supplied to drive circuits of inverters with respect to the respective control systems, thereby supplying drive currents from the inverters to the coil groups. The motor drive device detects a failure in any of the inverters and the coil groups with respect to each control system, and stops only the failed control system or causes only the failed control system to fall back. The motor drive device further includes a main computing device, and an auxiliary computing device. Consequently, if the auxiliary computing device is normal even in case the main computing device fails, driving of the motor can be continued using one or some of the control systems.