The present disclosure provides a battery detection device. The detection circuit is disposed on the battery and produces an impedance value variation quantity according to a deformation of the battery. The detection circuit includes four connection nodes. The first connection node and the third connection node are connected with the battery. A voltage variation quantity is produced between the second connection node and the fourth connection node according to the impedance value variation quantity. The protection circuit is connected with the second connection node and the fourth connection node. The protection circuit is in an ON state when the voltage variation quantity is greater than or equal to a cut-off voltage. The protection circuit is in an OFF state when the voltage variation quantity is less than the cut-off voltage, so that an operation state of the battery is changed accordingly.

The present disclosure provides a battery detection device. The detection circuit is disposed on the battery and produces an impedance value variation quantity according to a deformation of the battery. The detection circuit includes four connection nodes. The first connection node and the third connection node are connected with the battery. A voltage variation quantity is produced between the second connection node and the fourth connection node according to the impedance value variation quantity. The protection circuit is connected with the second connection node and the fourth connection node. The protection circuit is in an ON state when the voltage variation quantity is greater than or equal to a cut-off voltage. The protection circuit is in an OFF state when the voltage variation quantity is less than the cut-off voltage, so that an operation state of the battery is changed accordingly.

The present disclosure provides a battery protection device and a chip therein. The chip includes a buffer circuit and a switch circuit. The buffer circuit is configured to generate a gate control signal according to a first logic control signal, a first voltage, a second voltage, and a third voltage. The switch circuit is configured to transmit the second or the third voltage to the buffer circuit. The switch circuit includes an invert circuit and a select circuit. The invert circuit is configured to invert a second logic control signal to a third logic control signal. The select circuit is configured to select the second or third voltage to transmit the same to the buffer circuit according to the second logic control signal and the third logic control signal. The gate control signal is configured to turn off a power transistor when an overcharging or an over-discharging occurs.

The present disclosure provides a battery protection device and a chip therein. The chip includes a buffer circuit and a switch circuit. The buffer circuit is configured to generate a gate control signal according to a first logic control signal, a first voltage, a second voltage, and a third voltage. The switch circuit is configured to transmit the second or the third voltage to the buffer circuit. The switch circuit includes an invert circuit and a select circuit. The invert circuit is configured to invert a second logic control signal to a third logic control signal. The select circuit is configured to select the second or third voltage to transmit the same to the buffer circuit according to the second logic control signal and the third logic control signal. The gate control signal is configured to turn off a power transistor when an overcharging or an over-discharging occurs.

A management device 50 for power storage elements is provided with a cause analysis unit 51 that, when the voltages of power storage elements B1-B4 are reduced to a prescribed level or physical quantities correlated with the voltages are reduced to prescribed values after the supply of power to the power storage elements B1-B4 has been stopped, analyzes the cause of the voltage reduction in power storage elements B1-B4 or the cause of the reduction in the physical quantities correlated with voltages to the prescribed values, on the basis of measurement data of the power storage elements B1-B4 measured after the supply of power has been stopped.

The invention relates to an accumulator module (26) comprising a moisture-proof housing (28), in which a plurality of accumulator cells (31) is disposed, the contacts of which are electrically interconnected and which are routed to external contacts (30) of the accumulator module (26) disposed at the outer face of the housing (28). To be able to detect a short circuit between the external contacts (30) of the accumulator module (26) in the simplest and most efficient manner possible, it is proposed that a protection device (35) is disposed inside the housing (28), which protection device comprises a detection device (36), which is designed to detect a short circuit between the external contacts (30). Furthermore, the invention relates to a swimming and diving aid (10) comprising such an accumulator module (26).

The invention relates to an accumulator module (26) comprising a moisture-proof housing (28), in which a plurality of accumulator cells (31) is disposed, the contacts of which are electrically interconnected and which are routed to external contacts (30) of the accumulator module (26) disposed at the outer face of the housing (28). To be able to detect a short circuit between the external contacts (30) of the accumulator module (26) in the simplest and most efficient manner possible, it is proposed that a protection device (35) is disposed inside the housing (28), which protection device comprises a detection device (36), which is designed to detect a short circuit between the external contacts (30). Furthermore, the invention relates to a swimming and diving aid (10) comprising such an accumulator module (26).

Provided is a battery pack including a pair of output terminals, a control unit, and a plurality of battery units, where each of the plurality of battery units includes a plurality of battery blocks connected in series, a positive electrode terminal, and a negative electrode terminal, the battery block includes one battery or a plurality of batteries connected in parallel, a fuse is connected between at least one output terminal of the pair of output terminals and a positive electrode terminal or a negative electrode terminal corresponding to the one output terminal, and the fuse is allowed to be fused by the control unit.

The electrical system (100) includes: —a capacitor (C); —an electrical power supply device (102); —an electrical power receiving device (104); —a current-consuming electrical circuit (108) designed to consume a current (i) entering via a first interface terminal (B.sub.A) and exiting via a second interface terminal (B.sub.B). The electrical system (100) being designed such that the current-consuming electrical circuit (108) consumes the discharge current (i) when the electrical power supply device (102) is connected to the terminals of the capacitor (C). The current-consuming electrical circuit (108) includes a transistor (Q1) arranged such that the consumed current (i) enters via a current input terminal (C1) of the transistor (Q1) and exits via a current output terminal (E1) of the transistor (Q1), and in that the current output terminal (E1) is connected to a control terminal (B1) of the transistor (Q1) in order to stabilize the transistor (Q1).

The electrical system (100) includes: —a capacitor (C); —an electrical power supply device (102); —an electrical power receiving device (104); —a current-consuming electrical circuit (108) designed to consume a current (i) entering via a first interface terminal (B.sub.A) and exiting via a second interface terminal (B.sub.B). The electrical system (100) being designed such that the current-consuming electrical circuit (108) consumes the discharge current (i) when the electrical power supply device (102) is connected to the terminals of the capacitor (C). The current-consuming electrical circuit (108) includes a transistor (Q1) arranged such that the consumed current (i) enters via a current input terminal (C1) of the transistor (Q1) and exits via a current output terminal (E1) of the transistor (Q1), and in that the current output terminal (E1) is connected to a control terminal (B1) of the transistor (Q1) in order to stabilize the transistor (Q1).