A system of surge suppressor units is connected at multiple locations on a power transmission and distribution grid to provide grid level protection against various disturbances before such disturbances can reach or affect facility level equipment. The surge suppressor units effectively prevent major voltage and current spikes from impacting the grid. In addition, the surge suppressor units include various integration features which provide diagnostic and remote reporting capabilities required by most utility operations. As such, the surge suppressor units protect grid level components from major events such as natural geomagnetic disturbances (solar flares), extreme electrical events (lightning) and human-generated events (EMPs) and cascading failures on the power grid.

A system of surge suppressor units is connected at multiple locations on a power transmission and distribution grid to provide grid level protection against various disturbances before such disturbances can reach or affect facility level equipment. The surge suppressor units effectively prevent major voltage and current spikes from impacting the grid. In addition, the surge suppressor units include various integration features which provide diagnostic and remote reporting capabilities required by most utility operations. As such, the surge suppressor units protect grid level components from major events such as natural geomagnetic disturbances (solar flares), extreme electrical events (lightning) and human-generated events (EMPs) and cascading failures on the power grid.

An electrical wiring device including a ground fault interrupt assembly, the ground fault interrupt assembly comprising a ground fault interrupt circuit, being formed on a first printed circuit board, and a trip mechanism, the ground fault interrupt circuit being configured to detect a differential current between the line conductor and the neutral conductor and to trigger the trip mechanism to electrically decouple the plurality of line terminals from the plurality of load terminals, according to a predetermined criterion, based, at least in part, on the different current; and a USB power supply circuit being formed on a second printed circuit board disposed within the compartment, the USB power supply circuit providing to the at least one USB port, wherein the first printed circuit board and the second printed circuit board are separated by a distance within the inner compartment.

A radio frequency integrated circuit (RFIC) device includes: a first RF input/output (I/O) terminal; a second RF I/O terminal, where the first and the second RF I/O terminals are configured to transmit or receive an RF signal; a capacitor coupled between the first and the second RF I/O terminals; a first coil coupled between the first and the second RF I/O terminals, where the first coil is configured to provide ESD protection to the capacitor during a first ESD event; and a fast transient ESD protection circuit coupled between the first and the second RF I/O terminals, where the fast transient ESD protection circuit is configured to provide ESD protection to the capacitor during a second ESD event different from the first ESD event, where a first rise time of the first ESD event is longer than a second rise time of the second ESD event.

High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.

An arrangement for an overvoltage protection of a subsea electrical apparatus and a method for operating it. The arrangement includes a tank submersible below a water surface level, an electrical apparatus accommodated in the tank, and a surge arrester arrangement accommodated in the tank and coupled to a power supply of the electrical apparatus in the tank for providing the overvoltage protection of the electrical apparatus. The arrangement further includes a controllable grounding switch for connecting the surge arrester arrangement to a ground point in response to a control of the grounding switch to a closed state and for disconnecting the surge arrester arrangement from the ground point in response to a control of the grounding switch to an open state.

Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

An apparatus includes a first diode and a second diode connected in series between a first voltage terminal and a second voltage terminal, a switch connected between the first voltage terminal and the second voltage terminal, and a clamping threshold circuit connected between a common node of the first diode and the second diode, and a gate of the switch, wherein the clamping threshold circuit is configured such that in response to a voltage surge applied to the common node of the first diode and the second diode, the switch is turned on once the voltage surge is greater than a predetermined threshold.

Provided is an inrush current limiter and a system including the same, the inrush current limiter including first and second input nodes for receiving an input voltage from a power source, a first output node and a second output node for being connected with a load, an inrush-current-limiting portion including a transistor connected between the first input node and the first output node, and for turning on the transistor when a voltage level of the input voltage is higher than a first level, and for limiting an inrush current by controlling time until the transistor is turned on after application of the input voltage, a switch connected between a control terminal of the transistor and the second input node, and a mode controller for turning on the switch when the voltage level of the input voltage is lower than a second level that is lower than the first level.

A detector circuit included in a computer system filters the voltage level of a power supply node to generate filtered signals. The detector circuit either compares the filtered signals or samples the filtered signal and compares the samples to reference levels to detect changes in the voltage level of the power supply node that exceed thresholds for magnitude and duration. A control circuit included in the computer system generates, using the glitch signal, control signals that can be used to change operating parameters of functional circuits included in the computer system.