Disclosed herein is an overcurrent protection circuit configured to, upon detection of an output current that flows through a switch element reaching a first overcurrent limit value, reduce an overcurrent limit value for the output current from the first overcurrent limit value to a second overcurrent limit value smaller than the first overcurrent limit value.

Provided is a current limiting circuit (30) configured to: before release of a touch between a second contact (20b) provided at a position where a terminal (11a) on a power receiving side in which a current flows at supply of DC power in an electrode that supplies the DC power touches before touching a first contact (20a) provided for the electrode at supply of the DC power and the terminal (11a), decrease the current flowing into the terminal (11a) through the second contact (20b); and avoid flowing a current in a case where the terminal (11a) is touching the first contact (20a), and decrease the current flowing into the terminal (11a) through the second contact (20b) only in a case where the terminal (11a) is touching the second contact (20b).

A protection and attenuation circuit for sensitive AC loads is described. The circuit provides AC power protection and attenuation utilizing high-efficiency switch-mode techniques to attenuate an AC power signal by incorporating a bidirectional, transistorized switch driven from a pulse width modulation signal, PWM. The circuit monitors characteristics of the AC power signal driving a known load and characteristics of the load or other elements and determines the duty cycle of the pulse width modulated signal, PWM, based upon the duration and amplitude of the over-voltage, over-current, over-limit or other event.

There has been a problem in semiconductor apparatuses of related art in which a circuit operation cannot be returned after a reverse current occurred. In one embodiment, a semiconductor apparatus includes a timer block configured to count up a count value to a predetermined value in response to a control signal being enabled, the control signal instructing a power MOS transistor to be turned on, and a protection transistor including a drain connected to a gate of the power MOS transistor, a source and a back gate connected to a source of the power MOS transistor, and an epitaxial layer in which the power MOS transistor is formed, the epitaxial layer being supplied with a power supply voltage. The protection transistor short-circuits the source and gate of the power MOS transistor in response to an output voltage of the power MOS transistor meeting a predetermined condition and the count value reaching the predetermined value. The timer block resets the count value when the output voltage of the power MOS transistor no longer meets the predetermined condition.

An electronic fuse for a power supply includes at least two switching elements and a regulation unit, wherein a first switching element is arranged in a main branch, where the regulation unit is switches off the first switching element when a predetermined threshold value is exceeded by a prevailing current value, and a second switching element that is also actuated by the regulation unit, which is arranged in an auxiliary branch parallel to the first switching element and assumes a substantial proportion of a resulting power loss when an overload occurs, and the second switching element, which is arranged in at least one auxiliary branch, is configured or optimized for linear operation, and where the at least two switching elements are configured such that the line resistance of the second switching element is at least twice the line resistance of the first switching element.

A protection function of an electronic device is realized with a lower cost. A load drive circuit 102 includes: transistors Qa and Qb for protection of an N-channel type connected between a power source terminal P1 and a power source end P7 for driving; an inverter circuit 14 that drives a load based on an input drive control signal Sd, the inverter circuit 14 being disposed between the power source end P7 for driving and a ground potential; and a booster unit 16 including a capacitor C1 having one terminal connected to an output end of the inverter circuit 14, the booster unit 16 generating, across another terminal of the capacitor C1, a voltage exceeding a power source voltage Vdc, and applying the voltage to control electrodes of the transistors Qa and Qb for protection.

A device comprises a processor, a memory for storing instruction code that is executable by the processor, and power supply circuitry. The power supply circuitry is in communication with the processor. The power supply circuitry comprises voltage regulator circuitry, a capacitor, a current limiter, and a switch. The voltage regulator circuitry comprises an input electrically coupled to a voltage source and an output configured to provide a regulated voltage output. The capacitor is configured to store energy derived from the voltage source. The capacitor comprises a first node electrically coupled with the output of the voltage regulator circuitry. The current limiter is in electrical communication with a second node of the capacitor and configured to limit inrush current through the capacitor during a start-up phase of the power supply circuitry. The switch circuit is in electrical communication with the second node of the capacitor. Capacitor current flows through the switch when the switch circuit is in an ON state, substantially bypassing the current limiter. The switch is transitioned to the ON state when a particular control signal is applied to the switch circuit. The switch circuit is configured to remain in the ON state when the particular control signal is no longer applied to the switch circuit.

An electrostatic discharge (ESD) device with fast response to high transient currents. The ESD device includes a short-pulse discharge (SPD) path and a long-pulse discharge (LPD) path. The SPD path provides robust response to ESD events, and it triggers a self-bias configuration of the LPD path. Advantageously, the SPD path reduces the risk of ESD voltage overshoot by promptly discharging short-pulse currents, such as a charge device model (CDM) current, whereas the LPD path provides efficient discharge of long-pulse currents, such as a human body model (HBM) current. In one implementation, for example, the SPD path includes a MOS transistor, and the LPD includes a bipolar transistor having a base coupled to the source of the MOS transistor.

An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.

Embodiments of a single event latch-up (SEL) protection circuit are provided, including: a first circuitry block coupled to a source of an input voltage a load, and digitally controlling a first switch; the first switch generates a load and senses an instantaneous load current iLoad. A second circuitry block is configured to generate an average iLoad and generate single event latch-up triggers (i.e., SEL fault detection) as a function of at least a comparison of the inst_iLoad and average iLoad; wherein this first circuitry block contains the analog based SET filtering needed to reduce false SEL triggers. A supervisor module generates on/off commands for the first switch, responsive to receiving the SEL detection in excess of a pre-programmed delay to provide the final SET filtering to prevent false SEL triggers. The first circuitry block removes the load voltage at N1 upon receiving an off command from the supervisor module.