Disclosed herein is a modular, scalable, and galvanically isolated power electronics converter topology for medium voltage AC (MVAC) to DC or high voltage AC (HVAC) to DC power conversion. A disclosed modular converter can comprise a low-voltage direct current bus and a centralized controller configured to regulate the low-voltage direct current bus. The modular converter can further comprise a plurality of three-phase blocks connected in series. Individual three-phase blocks of the plurality of three-phase blocks can comprise a plurality of single-phase modules connected in an input-series output-parallel configuration. The modular converter can further comprise a filter connected between a grid input and the plurality of three-phase blocks and a pulse-width modulator configured to generate encoded gate pulses for the individual three-phase blocks of the plurality of three-phase blocks.

A voltage regulator having a multi-level, multi-phase architecture is disclosed. The circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level.

A voltage regulator having a multi-level, multi-phase architecture is disclosed. The circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level.

Systems and methods of this disclosure use low voltage energy storage devices to supply power at a medium voltage from an uninterruptible power supply (UPS) to a data center load. The UPS includes a low voltage energy storage device (ultracapacitor/battery), a high frequency (HF) bidirectional DC-DC converter, and a multi-level (ML) inverter. The HF DC-DC converter uses a plurality of HF planar transformers, multiple H-bridge circuits, and gate drivers for driving IGBT devices to generate a medium DC voltage from the ultracapacitor/battery energy storage. The gate drivers are controlled by a zero voltage switching (ZVS) controller, which introduces a phase shift between the voltage on the primary and secondary sides of the transformers. When the primary side leads the secondary side, the ultracapacitor/battery discharges and causes the UPS to supply power to the data center, and when the secondary side leads the primary side, power flows from the grid back to the UPS, thereby recharging the ultracapacitor/battery.

Systems and methods of this disclosure use low voltage energy storage devices to supply power at a medium voltage from an uninterruptible power supply (UPS) to a data center load. The UPS includes a low voltage energy storage device (ultracapacitor/battery), a high frequency (HF) bidirectional DC-DC converter, and a multi-level (ML) inverter. The HF DC-DC converter uses a plurality of HF planar transformers, multiple H-bridge circuits, and gate drivers for driving IGBT devices to generate a medium DC voltage from the ultracapacitor/battery energy storage. The gate drivers are controlled by a zero voltage switching (ZVS) controller, which introduces a phase shift between the voltage on the primary and secondary sides of the transformers. When the primary side leads the secondary side, the ultracapacitor/battery discharges and causes the UPS to supply power to the data center, and when the secondary side leads the primary side, power flows from the grid back to the UPS, thereby recharging the ultracapacitor/battery.

This application provides a power rectification method and apparatus, to supply power to a load by using a power supply capacity gap formed by a communications power that is at an existing network site, thereby achieving a capacity increase. The method includes: obtaining a total input current of each of three phase lines; and when it is determined that a total input current of at least one of the three phase lines is greater than a total input current threshold corresponding to the at least one phase line, adjusting a rectifier connected to the at least one phase line to reduce a total input power of the at least one phase line, so that the total input current of the at least one phase line is less than or equal to the total input current threshold corresponding to the at least one phase line.

A multiphase buck converter that includes smart two-phase power stages for reducing switching losses. Each of the smart power stages includes a first high side switch, a second high side switch, a first low side switch, a second low side switch, a switching capacitor, a first inductor, and a second inductor. The exemplary multiphase buck converter includes two such smart power stages and a multiphase controller for generating PWM signals for driving the two smart power stages synchronously.

The disclosure relates to an inverter for supplying a power provided as a DC voltage at a DC input to an AC mains connectable to an AC output. In this case, the inverter includes a switching network with a plurality of semiconductor switches and a digital control unit for producing a digital switching pattern for digitally operated semiconductor switches of the switching network that are able to be used to produce a first output voltage (U.sub.out,dig). The inverter additionally includes a linear control unit for producing signals for actuating at least one semiconductor switch of the switching network in a linear mode, wherein the linear control unit is set up to produce a voltage drop (U.sub.out,lin) across and/or a current (I.sub.out,lin) through the at least one linearly operated semiconductor switch to a target value that is dependent on an instantaneous difference between the first output voltage (U.sub.out,dig) and a voltage (U.sub.AC) of the AC mains. The disclosure additionally relates to a control method for such an inverter and a photovoltaic (PV) installation having such an inverter.

The disclosure relates to an inverter for supplying a power provided as a DC voltage at a DC input to an AC mains connectable to an AC output. In this case, the inverter includes a switching network with a plurality of semiconductor switches and a digital control unit for producing a digital switching pattern for digitally operated semiconductor switches of the switching network that are able to be used to produce a first output voltage (U.sub.out,dig). The inverter additionally includes a linear control unit for producing signals for actuating at least one semiconductor switch of the switching network in a linear mode, wherein the linear control unit is set up to produce a voltage drop (U.sub.out,lin) across and/or a current (I.sub.out,lin) through the at least one linearly operated semiconductor switch to a target value that is dependent on an instantaneous difference between the first output voltage (U.sub.out,dig) and a voltage (U.sub.AC) of the AC mains. The disclosure additionally relates to a control method for such an inverter and a photovoltaic (PV) installation having such an inverter.

A voltage regulator having a multi-level, multi-phase architecture is disclosed. The circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level.