A first controller for a power converter, the first controller comprising a driver, supply terminal, branch switch and branch control. The driver configured to provide a drive signal to turn ON and turn OFF a power switch. The power switch includes a first switch and a second switch coupled in a cascode configuration. The supply terminal coupled to a bypass capacitor that provides operating power to the first controller, wherein the bypass capacitor has a bypass voltage. The branch switch coupled to a node between the first switch and the second switch. The branch control configured to receive a regulation signal representative of a comparison of the bypass voltage to a bypass reference and is configured to turn ON the branch switch if the bypass voltage is below the bypass reference to redirect at least a portion of a drain current of the power switch to the bypass capacitor.

A first controller for a power converter, the first controller comprising a driver, supply terminal, branch switch and branch control. The driver configured to provide a drive signal to turn ON and turn OFF a power switch. The power switch includes a first switch and a second switch coupled in a cascode configuration. The supply terminal coupled to a bypass capacitor that provides operating power to the first controller, wherein the bypass capacitor has a bypass voltage. The branch switch coupled to a node between the first switch and the second switch. The branch control configured to receive a regulation signal representative of a comparison of the bypass voltage to a bypass reference and is configured to turn ON the branch switch if the bypass voltage is below the bypass reference to redirect at least a portion of a drain current of the power switch to the bypass capacitor.

The present application relates to a synchronous rectification sampling control circuit, method and chip. The control circuit includes a withstand voltage switch tube Q2, a power supply switch tube Q3, a positive phase power supply driving module, a detection control module, and a negative phase power supply module. The withstand voltage switch tube Q2 includes a withstand voltage source, a withstand voltage grid and a withstand voltage drain, in which the withstand voltage drain is configured to connect a secondary winding power supply circuit in a synchronous rectification circuit of a transformer to obtain a supply voltage and output a positive or negative sampling voltage at the withstand voltage source.

The present application relates to a synchronous rectification sampling control circuit, method and chip. The control circuit includes a withstand voltage switch tube Q2, a power supply switch tube Q3, a positive phase power supply driving module, a detection control module, and a negative phase power supply module. The withstand voltage switch tube Q2 includes a withstand voltage source, a withstand voltage grid and a withstand voltage drain, in which the withstand voltage drain is configured to connect a secondary winding power supply circuit in a synchronous rectification circuit of a transformer to obtain a supply voltage and output a positive or negative sampling voltage at the withstand voltage source.

A voltage dividing capacitor circuit includes first capacitor through third capacitor dividers and first through fourth load capacitors. The first capacitor divider includes a first flying capacitor and a plurality of first switches connected in series between a first voltage node and a ground node, and is connected to a second voltage node. The second capacitor divider is connected to the first voltage node, the second voltage node, and a first intermediate voltage node. The third capacitor divider is connected to the second voltage node, the ground voltage node, and a second intermediate voltage node. The first through fourth load capacitors are connected in series between the first voltage node and the ground node. The second capacitor divider includes a second flying capacitor and a plurality of second switches connected in series between the first voltage node and the second voltage node.

A voltage dividing capacitor circuit includes first capacitor through third capacitor dividers and first through fourth load capacitors. The first capacitor divider includes a first flying capacitor and a plurality of first switches connected in series between a first voltage node and a ground node, and is connected to a second voltage node. The second capacitor divider is connected to the first voltage node, the second voltage node, and a first intermediate voltage node. The third capacitor divider is connected to the second voltage node, the ground voltage node, and a second intermediate voltage node. The first through fourth load capacitors are connected in series between the first voltage node and the ground node. The second capacitor divider includes a second flying capacitor and a plurality of second switches connected in series between the first voltage node and the second voltage node.

A method includes turning on a first group of switches of a switched capacitor converter in a battery charging system to establish a first conductive path, and configuring a system voltage at a system bus to charge a first flying capacitor to a predetermined voltage level through the first conductive path, wherein the predetermined voltage level is less than the system voltage, and turning on a second group of switches of the switched capacitor converter in the battery charging system to establish a second conductive path to charge a battery, wherein a sum of a voltage across the first flying capacitor and the system voltage is applied to the battery.

A switched-capacitor converter has a first and second terminal; a switched-capacitor ladder network having a plurality of serially connected first capacitors defining a plurality of flying capacitor nodes; a plurality of serially connected second capacitors defining a plurality of output capacitor nodes, wherein nodes of the flying capacitor nodes can be connected to nodes of the output capacitor nodes in a plurality of ladder converter configurations to perform a switched-capacitor ladder power conversion; and a switch matrix to connect the first terminal to different flying capacitor nodes and/or to connect any flying capacitor node to any other flying capacitor node or output capacitor node according to different switch configurations. Also, a switched-capacitor converter assembly may have a plurality of serially and/or parallel connected switched-capacitor reconfigurable switched-capacitor ladder converters. Methods for converting an input into an output voltage using a converter and for operating an assembly of converters are also provided.

A switched-capacitor converter has a first and second terminal; a switched-capacitor ladder network having a plurality of serially connected first capacitors defining a plurality of flying capacitor nodes; a plurality of serially connected second capacitors defining a plurality of output capacitor nodes, wherein nodes of the flying capacitor nodes can be connected to nodes of the output capacitor nodes in a plurality of ladder converter configurations to perform a switched-capacitor ladder power conversion; and a switch matrix to connect the first terminal to different flying capacitor nodes and/or to connect any flying capacitor node to any other flying capacitor node or output capacitor node according to different switch configurations. Also, a switched-capacitor converter assembly may have a plurality of serially and/or parallel connected switched-capacitor reconfigurable switched-capacitor ladder converters. Methods for converting an input into an output voltage using a converter and for operating an assembly of converters are also provided.

A power management circuit for fast average power tracking (APT) voltage switching is provided. The power management circuit includes a primary voltage circuit configured to generate an APT voltage based on an APT target voltage. However, the primary voltage circuit may be inherently slow in ramping up the APT voltage to the APT target voltage. As such, a secondary voltage circuit is provided in the power management circuit to help drive the APT voltage to a desired level by a defined temporal limit. Once the APT voltage reaches the desired level, the secondary voltage circuit will automatically shut off, while the primary voltage circuit continues operating at a selected duty cycle to maintain the APT voltage at the APT target voltage. By utilizing the secondary voltage circuit to quickly drive up the APT voltage, the power management circuit is capable of supporting dynamic power control under stringent switching delay budget.