A solid state light source driver circuit that operates in either a buck convertor or a boost convertor configuration is provided. The driver circuit includes a controller, a boost switch circuit and a buck switch circuit, each coupled to the controller, and a feedback circuit, coupled to the light source. The feedback circuit provides feedback to the controller, representing a DC output of the driver circuit. The controller controls the boost switch circuit and the buck switch circuit in response to the feedback signal, to regulate current to the light source. The controller places the driver circuit in its boost converter configuration when the DC output is less than a rectified AC voltage coupled to the driver circuit at an input node. The controller places the driver circuit in its buck converter configuration when the DC output is greater than the rectified AC voltage at the input node.

Provided are a power supply conversion device and a charging control method. The device includes: a transformer; a first rectifier circuit connected to a primary winding of the transformer used for converting a received alternating current into a first direct current, a voltage value of the first direct current being a first direct-current voltage, and the transformer used for converting the first direct-current voltage into a second direct-current voltage; a voltage converter connected to a secondary winding of the transformer and used for converting the second direct-current voltage to output a constant direct-current voltage or a pulsating direct-current voltage; and a controller connected to the first rectifier circuit and the voltage converter and used for controlling the voltage converter to selectably output the constant direct-current voltage or the pulsating direct-current voltage according to a desired charging mode of a device to be charged connected to the power supply conversion device.

A control circuit for a power factor correction (PFC) circuit, the control circuit includes a multiplier having first, second, and third multiplier inputs and a multiplier output. The control circuit has an adder having first and second inputs and an output. The first input of the adder is coupled to the multiplier output. The control circuit further includes a root mean square (RMS) calculation circuit configured to determine a square of a root mean square of an input sinusoidal voltage. The RMS calculation circuit has an output coupled to the second multiplier input. An input voltage square calculation circuit is configured to determine a square of the input sinusoidal voltage. The input voltage square calculation circuit has an output coupled to the third multiplier input.

A method involves controlling, for a duration of a first modulation period, a first average off-time of a main switch of a power converter such that the first average off-time of the main switch corresponds to a first intermediate valley number of multiple intermediate valley numbers, an average of the intermediate valley numbers corresponding to a target number of valleys of a resonant waveform at a drain node of the main switch. A second intermediate valley number of the intermediate valley numbers is selected upon expiration of the first modulation period. A difference of the second intermediate valley number and the first intermediate valley number is equal to a fractional valley number offset. A second average off-time of the main switch is controlled for a duration of a second modulation period such that the second average off-time of the main switch corresponds to the second intermediate valley number.

There is described a power supply unit having at least one alternating current (AC) input and at least one direct current (DC) output for producing an output voltage. The power supply unit comprises at least one input transformer coupled to the at least one AC input and at least one rectification circuit defining an AC side and a DC side, and coupled to the at least one input transformer on the AC side. The at least one rectification circuit comprises a diode rectifier section on the AC side comprising at least one set of diode rectifiers, and a controlled rectifier section in series with the diode rectifier section and configured for producing a variable load voltage to modulate the output voltage between a base voltage and a maximum value of the output voltage using at least one set of three single-phase controlled rectifiers usable as one to three DC outputs to form a three-phase controlled rectifier.

A method for controlling an electric load is described herein. In accordance with one embodiment the method includes collecting ambient energy using an energy harvesting circuit and using the collected ambient energy to charge a buffer capacitor. The method further includes alternatingly connecting and disconnecting an electrical load and the buffer capacitor, wherein a capacitor voltage provided by the buffer capacitor is applied to the electrical load in a discharging phase, in which the electrical load is connected to the buffer capacitor and the capacitor voltage decreases, and wherein the buffer capacitor is recharged in a charging phase, in which the electrical load is disconnected from the buffer capacitor in a charging phase in which the capacitor voltage again increases. The durations of the charging phase and the discharging phase are designed such that the capacitor voltage stays above a minimum supply voltage of the electrical load.

A control circuit for a power factor correction (PFC) circuit, the control circuit includes a multiplier having first, second, and third multiplier inputs and a multiplier output. The control circuit has an adder having first and second inputs and an output. The first input of the adder is coupled to the multiplier output. The control circuit further includes a root mean square (RMS) calculation circuit configured to determine a square of a root mean square of an input sinusoidal voltage. The RMS calculation circuit has an output coupled to the second multiplier input. An input voltage square calculation circuit is configured to determine a square of the input sinusoidal voltage. The input voltage square calculation circuit has an output coupled to the third multiplier input.

A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.

Provided is a system for an insulated-gate bipolar transistor (IGBT) rectifier for charging ultra-capacitors. The system may include a power converter, which may receive power from a power source. A direct current (DC) bus may be connected to the power converter and may receive power from the power converter. At least one IGBT may be connected to the DC bus and may receive power from the DC bus. An array of ultra-capacitors may be connected to the at least one IGBT. At least one controller may control the at least one IGBT to charge the array of ultra-capacitors. A method and computer program product are also disclosed.

An AC to DC conversion system is described. The conversion system consists of an electronic switch and control circuitry employed to provide controlled pulsed power to a storage device that provides power to a load at either a preselected or manually or automatic selectable voltages while ensuring the voltage drop across the switch is minimized to reduce power dissipated through the switch itself, thereby significantly increasing the efficiency and reducing thermal losses. The AC to DC converter in one minimal version consists of a pair of N-MOSFET transistors, a voltage divider, a storage element and a pair of diodes. The design enables high efficiency with minimal components that may be fully integrated onto silicon.