A voltage dividing capacitor circuit includes first capacitor through third capacitor dividers and first through fourth load capacitors. The first capacitor divider includes a first flying capacitor and a plurality of first switches connected in series between a first voltage node and a ground node, and is connected to a second voltage node. The second capacitor divider is connected to the first voltage node, the second voltage node, and a first intermediate voltage node. The third capacitor divider is connected to the second voltage node, the ground voltage node, and a second intermediate voltage node. The first through fourth load capacitors are connected in series between the first voltage node and the ground node. The second capacitor divider includes a second flying capacitor and a plurality of second switches connected in series between the first voltage node and the second voltage node.

A power switching circuit including a first DC/DC converter having a first input configured to receive a first input DC voltage, a second DC/DC converter having a first input configured to receive a second input DC voltage, a DC/AC inverter having a first input coupled to the output of the first DC/DC converter and a second input coupled to the output of the second DC/DC converter, the DC/AC inverter including n (n>2) switching legs, and at least one controller coupled to the first DC/DC converter, the second DC/DC converter, and the DC/AC inverter, the at least one controller configured to operate the DC/AC inverter to provide n AC signals to at least one load coupled to the DC/AC inverter by operating two of the n switching legs in a static state and n−2 of the n switching legs in a transition state.

Driver circuitry for driving a load based on an input signal, comprising: at least one variable boost stage comprising: first and second input nodes configured to receive a first voltage and a second voltage respectively; first and second flying capacitor nodes for connection to a flying capacitor therebetween; a network of switching paths for selectively connecting the first and second input nodes with the first and second flying capacitor nodes; an output stage for selectively connecting a driver output node to each of the first and second flying capacitor nodes; and a controller operable in a first boost mode to: control the output stage to selectively connect the driver output node to the first flying capacitor node; control the network of switching paths to switch connection of the second flying capacitor node between the first and second input nodes at a controlled duty cycle; and in a first charge top-up cycle, control the network of switching paths to connect the first input node to the first flying capacitor node during a phase of the controlled duty cycle in which the first input node is connected to the second flying capacitor node; wherein the frequency of the controlled duty cycle is greater than the frequency of the charge top-up cycle.

A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.

A loss optimization control method for modular multilevel converters (MMCs) under fault-tolerant control is disclosed. The method includes the following steps: when a fault of a SM in a MMC occurs, bypassing the faulty SM to achieve fault-tolerant control; suppressing the fundamental circulating current using a fundamental circulating current controller; respectively calculating the loss of each SM in faulty arms and healthy arms by using loss expressions of different switching tubes in SMs of the MMC; aiming at the loss imbalance between the arms of the MMC, taking the loss of a healthy SM as the reference, adjusting the period of capacitor voltage sorting control in the faulty SMs, achieving the loss control over the working SMs in the faulty SMs, and finally achieving the loss balance of each SM in the faulty arms and the healthy arms. Compared with the conventional methods, the proposed method is easier to implement and does not increase the construction cost of MMCs.

An AC-DC converter may include three phase terminals, two DC terminals, a first converter stage to convert between an AC current at the phase terminals and a first DC current at the first and second intermediate nodes, a second converter stage operable to convert between a first DC signal at third and fourth intermediate nodes and a second DC signal at the DC terminals, a first filter stage comprising a capacitor network having a star-point, a DC link connecting the first intermediate node to the third intermediate node and the second intermediate node to the fourth intermediate node. The second converter stage includes a middle voltage node between the DC terminals and a boost circuit having a midpoint node at the same electrical potential as the middle voltage node. The DC link includes a common mode filter having a common mode capacitor connecting the middle voltage node to the star-point.

Aspects are described for hybrid modular multilevel converters that include half-bridge submodules. In some embodiments, a hybrid modular multilevel converter can include a direct current (DC) bus and an alternating current (AC) node. A first arm of the hybrid modular multilevel converter includes a first submodule chain link and a first arm inductor and a second arm includes a second submodule chain link and a second arm inductor. A capacitor connects between a first side of the first arm and a first side of the second arm.

Described embodiments include a circuit for limiting power converter output ripple. A first transistor has a first current terminal receiving an input voltage, and a second current terminal coupled to a first capacitor. A second transistor has a third current terminal coupled to the first capacitor, and a fourth current terminal is coupled to a second capacitor. A third transistor has a fifth current terminal coupled to the second capacitor, and a sixth terminal coupled to a filter input. A fourth transistor has a seventh current terminal coupled to the second current terminal, and an eighth current terminal coupled to the sixth current terminal. A fifth transistor has a ninth current terminal coupled to the fourth current terminal, and a tenth current terminal coupled to the sixth current terminal.

A protection circuit for a power converter with cascaded bipolar and/or unipolar semiconductors is provided. The protection circuit includes at least one comparator circuit which is adapted to monitor a voltage characteristic on a collector-emitter path of at least one semiconductor which is arranged in a polarity selection stage of the power converter and/or to monitor a voltage characteristic on at least one capacitor, which is arranged in the power converter. The at least one comparator circuit is further adapted to output an electrical signal, representing the voltage characteristic of the semiconductor and/or the at least one capacitor to at least one evaluation unit. The at least one evaluation unit is further adapted to evaluate the result from the at least one comparator circuit and to deactivate the semiconductors in case that the voltage characteristic of the semiconductors and/or the capacitors deviate from a predetermined threshold.

Techniques and apparatus for current-based transitioning between a buck converter mode and a charge pump mode in an adaptive combination power supply circuit. One example power supply circuit generally includes a switching regulator and control logic coupled to the switching regulator. The control logic is generally configured to compare an indication of a current associated with the switching regulator to a threshold and to control a transition of the switching regulator between a buck converter mode and a charge pump mode based on the comparison.