Described herein is a method of operating a power electronic converter device for an electrical power conversion system. The power electronic converter device includes a converter circuit including an input side, an output side, a first converter, and at least one second converter. The second converter includes at least one floating cell with a DC intermediate circuit and semiconductor devices. The method includes: switching the semiconductor devices of the floating cell at switching instants determined with optimized pulse patterns or carrier-based pulse width modulation; determining a fundamental voltage component for the floating cell; and generating the fundamental voltage component in the actual voltage of the floating cell by modifying the switching instants, such that a voltage V.sub.C AF of the DC intermediate circuit is lying in a given reference voltage range for balancing the DC intermediate circuit of the floating cell.

Described herein is a method of operating a power electronic converter device for an electrical power conversion system. The power electronic converter device includes a converter circuit including an input side, an output side, a first converter, and at least one second converter. The second converter includes at least one floating cell with a DC intermediate circuit and semiconductor devices. The method includes: switching the semiconductor devices of the floating cell at switching instants determined with optimized pulse patterns or carrier-based pulse width modulation; determining a fundamental voltage component for the floating cell; and generating the fundamental voltage component in the actual voltage of the floating cell by modifying the switching instants, such that a voltage V.sub.C AF of the DC intermediate circuit is lying in a given reference voltage range for balancing the DC intermediate circuit of the floating cell.

A semiconductor device including: NMOS transistors respectively having the drains, which are connectable to respective second terminals of boot capacitors of which respective first terminals are connectable to respective nodes at which high-side transistors and the low-side transistors are connected together, and the sources, which are electrically connectable to an application terminal for a supply voltage; and controllers driving respective gates of the plurality of NMOS transistors. When the high-side transistor for a first channel is kept off by the driver for the first channel, the high-side transistor for a second channel, which is different from the first channel, is kept on by the driver for the second channel. The controller for the first channel feeds a drive voltage based on the boot voltage for the second channel to the gate of the NMOS transistor for the first channel to keep on the NMOS transistor.

A semiconductor device including: NMOS transistors respectively having the drains, which are connectable to respective second terminals of boot capacitors of which respective first terminals are connectable to respective nodes at which high-side transistors and the low-side transistors are connected together, and the sources, which are electrically connectable to an application terminal for a supply voltage; and controllers driving respective gates of the plurality of NMOS transistors. When the high-side transistor for a first channel is kept off by the driver for the first channel, the high-side transistor for a second channel, which is different from the first channel, is kept on by the driver for the second channel. The controller for the first channel feeds a drive voltage based on the boot voltage for the second channel to the gate of the NMOS transistor for the first channel to keep on the NMOS transistor.

A control method of a three-phase multi-level inverter includes: determining a modulation ratio based on output of the three-phase multi-level inverter, where the modulation ratio indicates a ratio of an amplitude value of a sinusoidal modulation wave in pulse width modulation to an amplitude value of a carrier; generating, based on the modulation ratio and a modulation ratio threshold, a common-mode voltage regulation signal for regulating a common-mode voltage in phase voltages of the three-phase multi-level inverter; adding the common-mode voltage regulation signal and a differential-mode voltage regulation signal for regulating a differential-mode voltage in the phase voltages of the three-phase multi-level inverter to obtain a composite regulation signal, where the composite regulation signal is presented as a modulation wave for discontinuous pulse width modulation (DPWM); and generating, based on the composite regulation signal, drive signals for controlling switches of phases of the three-phase multi-level inverter.

The present disclosure provides step-down rectifier circuit includes a rectifier module, a charge pump module, a filter unit, and a control unit. The rectifier module includes a first bridge arm unit connected to in-phase output terminal of an alternating current signal and a second bridge arm unit connected to out-of-phase output terminal of the alternating current signal. The charge pump module includes a first voltage converter unit and a second voltage converter unit in parallel. The control unit is configured to output a first pulse width modulation signal to control the on and off of the switch transistors in the rectifier module, and output a second pulse width modulation signal to control the on and off of the switch transistors in the charge pump module, such that an operating frequency of the charge pump module is a positive integer multiple of the frequency of the alternating current signal.

The present disclosure provides step-down rectifier circuit includes a rectifier module, a charge pump module, a filter unit, and a control unit. The rectifier module includes a first bridge arm unit connected to in-phase output terminal of an alternating current signal and a second bridge arm unit connected to out-of-phase output terminal of the alternating current signal. The charge pump module includes a first voltage converter unit and a second voltage converter unit in parallel. The control unit is configured to output a first pulse width modulation signal to control the on and off of the switch transistors in the rectifier module, and output a second pulse width modulation signal to control the on and off of the switch transistors in the charge pump module, such that an operating frequency of the charge pump module is a positive integer multiple of the frequency of the alternating current signal.

The vibration and noise generated in a permanent magnet synchronous motor are effectively suppressed. A motor control device 1 comprises: a triangular wave generation unit 17 which generates a triangular wave signal Tr that is a carrier wave, a carrier frequency adjustment unit 16 which adjusts a carrier frequency fc that represents a frequency of the triangular wave signal Tr, and a gate signal generation unit 18 which performs pulse-width modulation on three-phase voltage commands Vu*, Vv*, Vw* according to a torque command T* using the triangular wave signal Tr, thereby generating a gate signal for controlling an operation of an inverter. The carrier frequency adjustment unit 16 adjusts the carrier frequency fc so as to change a voltage phase error Δθv representing a phase difference of the three-phase voltage commands Vu*, Vv*, Vw* and the triangular wave signal Tr based on the torque command T*, and a rotation speed ωr of a motor.

The vibration and noise generated in a permanent magnet synchronous motor are effectively suppressed. A motor control device 1 comprises: a triangular wave generation unit 17 which generates a triangular wave signal Tr that is a carrier wave, a carrier frequency adjustment unit 16 which adjusts a carrier frequency fc that represents a frequency of the triangular wave signal Tr, and a gate signal generation unit 18 which performs pulse-width modulation on three-phase voltage commands Vu*, Vv*, Vw* according to a torque command T* using the triangular wave signal Tr, thereby generating a gate signal for controlling an operation of an inverter. The carrier frequency adjustment unit 16 adjusts the carrier frequency fc so as to change a voltage phase error Δθv representing a phase difference of the three-phase voltage commands Vu*, Vv*, Vw* and the triangular wave signal Tr based on the torque command T*, and a rotation speed ωr of a motor.

Duty cycles of pulse width modulation (“PWM”) pulses are determined by measurements taken with respect to an internally generated clock signal. One of these measurements calculates, in a continuous dynamic manner, a ratio of the number of cycles of the internally generated clock signal to one or more cycles of a PWM clock signal utilized as a time base for generation of the PWM pulses. This clock ratio measurement designates how many cycles of the internally generated clock signal will be used to designate a first portion of a duty cycle for each PWM pulse. Another measurement is utilized to determine a fractional portion of a cycle of the internally generated clock signal that will be used to designate a second portion of the duty cycle for each PWM pulse.