Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

Aspects of this disclosure relate to a very low intermediate frequency (VLIF) receiver with multi-decade contiguous radio frequency (RF) band coverage. Non-quadrature local oscillator (LO) signals drive mixers. The non-quadrature signals can be generated from low noise digital dividers having non-traditional division ratios. The non-traditional division ratios can be prime number ratios such as 5 and 7. The systematic non-quadrature nature of the LO/mixer can be subsequently corrected by a deterministic I-Q coupling network prior to complex signal processing.

Certain aspects of the present disclosure provide a local oscillator (LO) for wireless communication. In some examples, the LO is configured to generate an LO signal by inverting, by a first inverter, a first signal to generate a second signal having a first frequency, the first signal being an oscillating signal. In some examples, the LO is configured to control, using a third signal having a second frequency, a first switch receiving the second signal. In some examples, the LO is configured to control, using a fourth signal having the second frequency, a second switch receiving the second signal, wherein the fourth signal is a complement of the third signal and wherein the second frequency is one-half the first frequency.

Certain aspects of the present disclosure provide a local oscillator (LO) for wireless communication. In some examples, the LO is configured to generate an LO signal by inverting, by a first inverter, a first signal to generate a second signal having a first frequency, the first signal being an oscillating signal. In some examples, the LO is configured to control, using a third signal having a second frequency, a first switch receiving the second signal. In some examples, the LO is configured to control, using a fourth signal having the second frequency, a second switch receiving the second signal, wherein the fourth signal is a complement of the third signal and wherein the second frequency is one-half the first frequency.

Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.

Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.

A frequency divider circuit includes an oscillator comprising a plurality of delay elements coupled in series with each other, a first coupling circuit coupled to a first oscillator node and including a control terminal to receive a first retiming signal, and a first multiplexer including inputs coupled to receive the input signal and a complementary input signal, a control terminal coupled to a second oscillator node, and an output to provide the first retiming signal. The first multiplexer may be configured to alternate between injecting the input signal into the first oscillator node based on rising edges of the input signal and injecting the input signal into the first oscillator node based on falling edges of the input signal in response to a logic state of an oscillation waveform appearing at the second oscillator node.

A frequency divider circuit includes an oscillator comprising a plurality of delay elements coupled in series with each other, a first coupling circuit coupled to a first oscillator node and including a control terminal to receive a first retiming signal, and a first multiplexer including inputs coupled to receive the input signal and a complementary input signal, a control terminal coupled to a second oscillator node, and an output to provide the first retiming signal. The first multiplexer may be configured to alternate between injecting the input signal into the first oscillator node based on rising edges of the input signal and injecting the input signal into the first oscillator node based on falling edges of the input signal in response to a logic state of an oscillation waveform appearing at the second oscillator node.

Aspects of this disclosure relate to a very low intermediate frequency (VLIF) receiver with multi-decade contiguous radio frequency (RF) band coverage. Non-quadrature local oscillator (LO) signals drive mixers. The non-quadrature signals can be generated from low noise digital dividers having non-traditional division ratios. The non-traditional division ratios can be prime number ratios such as 5 and 7. The systematic non-quadrature nature of the LO/mixer can be subsequently corrected by a deterministic I-Q coupling network prior to complex signal processing.

A frequency divider circuit (200) includes a frequency sub-divider (201) to provide a frequency divided clock, a delay circuit (250) configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit (202) configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.