The present disclosure relates to integrated circuits. One example integrated circuit includes a first resonant circuit, a second resonant circuit, and at least one connection circuit. The first resonant circuit includes a first inductor, and the second resonant circuit includes a second inductor. The first inductor includes a first port, and the second inductor includes a second port. The at least one connection circuit is connected between the first port and the second port. The at least one connection circuit provides an electrical connection between the first port and the second port.

The present disclosure relates to integrated circuits. One example integrated circuit includes a first resonant circuit, a second resonant circuit, and at least one connection circuit. The first resonant circuit includes a first inductor, and the second resonant circuit includes a second inductor. The first inductor includes a first port and a second port, and the second inductor includes a third port and a fourth port. The at least one connection circuit is connected between at least one of the first port and the second port and at least one of the third port and the fourth port. Each connection circuit of the at least one connection circuit provides an electrical connection between two ports, where each of the two ports is connected to the connection circuit.

The present disclosure relates to integrated circuits. One example integrated circuit includes a first resonant circuit, a second resonant circuit, and at least one connection circuit. The first resonant circuit includes a first inductor, and the second resonant circuit includes a second inductor. The first inductor includes a first port, and the second inductor includes a second port. The at least one connection circuit is connected between the first port and the second port. The at least one connection circuit provides an electrical connection between the first port and the second port.

The present disclosure relates to integrated circuits. One example integrated circuit includes a first resonant circuit, a second resonant circuit, and at least one connection circuit. The first resonant circuit includes a first inductor, and the second resonant circuit includes a second inductor. The first inductor includes a first port and a second port, and the second inductor includes a third port and a fourth port. The at least one connection circuit is connected between at least one of the first port and the second port and at least one of the third port and the fourth port. Each connection circuit of the at least one connection circuit provides an electrical connection between two ports, where each of the two ports is connected to the connection circuit.

An output buffer for an oscillator circuit and associated methodology. The output buffer has inverters and at least one negative feedback loop coupled to corresponding inverters. The negative feedback loop of the circuit is disabled in response to a control signal until one or more of a defined level of oscillation and a defined period of time is reached during start-up of the oscillator circuit, and is thereafter enabled. At least one of the inverters has at least one second negative feedback loop coupled to the corresponding inverter. An amount of feedback provided by the second negative feedback loop is adjustable in response to a control signal, where a first feedback level is present until a defined level of oscillation and/or a defined period of time is reached during start-up, a second feedback level is thereafter present in, and the first feedback level is less than the second feedback level.

An oscillator start-up circuit and methodology for oscillator start-up is disclosed. The circuit includes a reference bias switch coupled to a reference node and a load node of a transconductor of an oscillator. The reference bias switch is responsive to a control signal for start-up of the oscillator and operable to close at a first time prior to start-up of the oscillator to maintain a voltage at the reference node equal to a voltage at the load node prior to application of bias to the transconductor. The reference bias switch is further operable to open at a second time subsequent to the first time. In one embodiment, a separate reference bias voltage is applied to a reference node of the transconductor.

An oscillator bias stabilization circuit and method for biasing the circuit is disclosed. The bias stabilization circuit includes a plurality of resistive dividers responsive to a control signal in the circuit. The plurality of resistive dividers are selectably connectable in the circuit to provide an adaptable equivalent resistance in response to a control signal while keeping a bias voltage produced by the circuit substantially constant as the loop gain of an oscillator is varied. The plurality of resistive dividers are coupled to a node in the oscillator that establishes the bias voltage.

An oscillator start-up circuit and methodology for oscillator start-up is disclosed. The circuit includes a reference bias switch coupled to a reference node and a load node of a transconductor of an oscillator. The reference bias switch is responsive to a control signal for start-up of the oscillator and operable to close at a first time prior to start-up of the oscillator to maintain a voltage at the reference node equal to a voltage at the load node prior to application of bias to the transconductor. The reference bias switch is further operable to open at a second time subsequent to the first time. In one embodiment, a separate reference bias voltage is applied to a reference node of the transconductor.

An output buffer for an oscillator circuit and associated methodology. The output buffer has inverters and at least one negative feedback loop coupled to corresponding inverters. The negative feedback loop of the circuit is disabled in response to a control signal until one or more of a defined level of oscillation and a defined period of time is reached during start-up of the oscillator circuit, and is thereafter enabled. At least one of the inverters has at least one second negative feedback loop coupled to the corresponding inverter. An amount of feedback provided by the second negative feedback loop is adjustable in response to a control signal, where a first feedback level is present until a defined level of oscillation and/or a defined period of time is reached during start-up, a second feedback level is thereafter present in, and the first feedback level is less than the second feedback level.

An oscillator bias stabilization circuit and method for biasing the circuit is disclosed. The bias stabilization circuit includes a plurality of resistive dividers responsive to a control signal in the circuit. The plurality of resistive dividers are selectably connectable in the circuit to provide an adaptable equivalent resistance in response to a control signal while keeping a bias voltage produced by the circuit substantially constant as the loop gain of an oscillator is varied. The plurality of resistive dividers are coupled to a node in the oscillator that establishes the bias voltage.