The present disclosure provides an adaptive adjustment circuit in a computer chip having a voltage-controlled oscillator (VCO) and a processor. The adaptive adjustment circuit comprises a frequency difference acquisition module to generate a frequency difference signal based on a first difference between an oscillation frequency of the VCO and a target frequency. The adaptive adjustment circuit also includes a power module to supply a working voltage to the VCO and the processor, adjust the working voltage based on the frequency difference signal, and supply the adjusted working voltage to the VCO and the processor.

A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors. There is a first conduction path between the first terminal of the first transistor and the control terminal of the second transistor, and a second conduction path between the control terminal of the first transistor and the first terminal of the second transistor. The control terminal of at least one of the first and second transistors is biased by the control input signal, such that a parasitic capacitance of said at least one of the first and second transistors can be tuned by the control input signal, in order to tune the frequency of the output of the voltage controlled oscillator, and hence the frequency of oscillation of the phase-locked loop.

An oscillator includes a tunable oscillator, a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator, and an oscillator controller circuit configured to adjust frequency of the tunable oscillator based upon phase detection between output of the tunable oscillator and output of an external resonant element received at the input to the oscillator.

An oscillator circuit includes an oscillator transistor (Q1) having respective first, second, and control terminals, the oscillator transistor being arranged to generate a microwave oscillating signal at the first terminal. A surface integrated waveguide resonator (Y1) is connected to the second terminal of the oscillator transistor (Q1). An active bias circuit portion (202) including a negative feedback arrangement is between the first terminal of the oscillator transistor (Q1) and the control terminal of the oscillator transistor (Q1), the active bias circuit portion being arranged to supply a bias current to the control terminal of the oscillator transistor (Q1). The bias current is dependent on a voltage at the first terminal of the oscillator transistor (Q1) multiplied by a negative gain.

An oscillator circuit includes an amplifier including a first transconductance amplifier and a second transconductance amplifier; and a resonator including a capacitor element and an inductor element. The capacitor element includes a first capacitor and a second capacitor, the inductor element includes a tapped inductor, the tapped inductor includes a first segment of inductor and a second segment of inductor, and the first segment of inductor and the second segment of inductor are coupled using the first capacitor. The first segment of inductor includes a first terminal and a second terminal coupled to an input terminal and an output terminal of the first transconductance amplifier respectively. The second segment of inductor includes a third terminal and a fourth terminal coupled to an input terminal and an output terminal of the second transconductance amplifier, respectively.

An oscillator circuit includes an oscillator transistor (Q1) having respective first, second, and control terminals, the oscillator transistor being arranged to generate a microwave oscillating signal at the first terminal. A surface integrated waveguide resonator (Y1) is connected to the second terminal of the oscillator transistor (Q1). An active bias circuit portion (202) including a negative feedback arrangement is between the first terminal of the oscillator transistor (Q1) and the control terminal of the oscillator transistor (Q1), the active bias circuit portion being arranged to supply a bias current to the control terminal of the oscillator transistor (Q1). The bias current is dependent on a voltage at the first terminal of the oscillator transistor (Q1) multiplied by a negative gain.

The present disclosure provides an adaptive adjustment circuit in a computer chip having a voltage-controlled oscillator (VCO) and a processor. The adaptive adjustment circuit comprises a frequency difference acquisition module to generate a frequency difference signal based on a first difference between an oscillation frequency of the VCO and a target frequency. The adaptive adjustment circuit also includes a power module to supply a working voltage to the VCO and the processor, adjust the working voltage based on the frequency difference signal, and supply the adjusted working voltage to the VCO and the processor.

This application provides an oscillator circuit. The oscillator circuit includes: an amplifier, including a first transconductance amplifier, and a second transconductance amplifier; and a resonator, including a capacitor element and an inductor element. The capacitor element includes a first capacitor and a second capacitor, the inductor element includes a tapped inductor, the tapped inductor includes a first segment of inductor and a second segment of inductor, and the first segment of inductor and the second segment of inductor are coupled by using the first capacitor. The first segment of inductor includes a first terminal and a second terminal coupled to an input terminal and an output terminal of the first transconductance amplifier respectively. The second segment of inductor includes a third terminal and a fourth terminal coupled to an input terminal and an output terminal of the second transconductance amplifier respectively.

A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.

A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.