A relaxation oscillator includes a resistor-capacitor (RC) circuit, an integration capacitor, a sampling circuit, and a controllable oscillator. The RC circuit performs an RC charging operation to set a first voltage, performs an RC discharging operation to set a second voltage, and performs a reset operation to reset the first voltage to a first reference voltage and reset the second voltage to a second reference voltage. The sampling circuit performs a charge delivery operation to sample a voltage difference between the first voltage and the second voltage, and transfers the voltage difference to the integration capacitor. The controllable oscillator generates an output clock in response to a control input provided by the integration capacitor.

A relaxation oscillator includes a resistor-capacitor (RC) circuit, an integration capacitor, a sampling circuit, and a controllable oscillator. The RC circuit performs an RC charging operation to set a first voltage, performs an RC discharging operation to set a second voltage, and performs a reset operation to reset the first voltage to a first reference voltage and reset the second voltage to a second reference voltage. The sampling circuit performs a charge delivery operation to sample a voltage difference between the first voltage and the second voltage, and transfers the voltage difference to the integration capacitor. The controllable oscillator generates an output clock in response to a control input provided by the integration capacitor.

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

A relaxation oscillator includes a resistor-capacitor (RC) circuit, an integration capacitor, a sampling circuit, and a controllable oscillator. The RC circuit performs an RC charging operation to set a first voltage, performs an RC discharging operation to set a second voltage, and performs a reset operation to reset the first voltage to a first reference voltage and reset the second voltage to a second reference voltage. The sampling circuit performs a charge delivery operation to sample a voltage difference between the first voltage and the second voltage, and transfers the voltage difference to the integration capacitor. The controllable oscillator generates an output clock in response to a control input provided by the integration capacitor.

A relaxation oscillator includes a resistor-capacitor (RC) circuit, an integration capacitor, a sampling circuit, and a controllable oscillator. The RC circuit performs an RC charging operation to set a first voltage, performs an RC discharging operation to set a second voltage, and performs a reset operation to reset the first voltage to a first reference voltage and reset the second voltage to a second reference voltage. The sampling circuit performs a charge delivery operation to sample a voltage difference between the first voltage and the second voltage, and transfers the voltage difference to the integration capacitor. The controllable oscillator generates an output clock in response to a control input provided by the integration capacitor.

In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.

In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.

A low power relaxation oscillator circuit includes, in one embodiment, a first comparator for comparing voltages at first and second inputs, respectively, a first capacitor coupled to the first input of the first comparator, and a first circuit configured for charging the first capacitor to a first voltage. The first voltage is related to a propagation delay of the first comparator.

A low power relaxation oscillator circuit includes, in one embodiment, a first comparator for comparing voltages at first and second inputs, respectively, a first capacitor coupled to the first input of the first comparator, and a first circuit configured for charging the first capacitor to a first voltage. The first voltage is related to a propagation delay of the first comparator.