A radio communications system includes a transmitter and a receiver. The transmitter generates or receives digital symbols having a given symbol rate associated with a corresponding symbol period; and generates, every S digital symbols generated/received (S>3), a respective multi-mode digital signal, which has a predefined time length shorter than S times the symbol period, which is sampled with a predefined sampling rate higher than the symbol rate, and which carries the S digital symbols by a plurality of orthogonal harmonic modes including a main mode which is a real harmonic mode and carries P of the S digital symbols (P<S). The receiver receives and processes the radio frequency signal to obtain a corresponding incoming digital signal; and extracts, from successive, non-overlapped portions of the incoming digital signal sampled with the predefined sampling rate, the S digital symbols respectively carried by each incoming digital signal portion by the orthogonal harmonic modes.

A base station for generating multi-user precoders. The base station includes a transceiver configured to receive sounding reference signals (SRSs) from a set of user equipments (UEs), and a processor configured to select, for one or more UEs in the set of UEs, one or more codewords from an uplink codebook based on a correlation between the one or more codewords and the one or more SRSs; determine, using a composite downlink codebook, downlink codewords for the selected uplink codewords, respectively, the composite downlink codebook mapping uplink codewords to downlink codewords based on steering angles derived from the uplink codewords; transmit a set of pre-coded channel state information reference signals (CSI-RSs) to the one or more UEs, wherein the pre-coded CSI-RSs are pre-coded based on the determined downlink codewords; and identify a downlink channel matrix based on CSI feedback from the one or more UEs and the pre-coded CSI-RSs.

A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLF.sub.INV(s). The VLF.sub.INV(s) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a −3-dB corner frequency of 40 MHz.

An apparatus and a method. The apparatus includes an interference mitigation processor, including an input, and an output, the interference mitigation processor configured to sum n msec received correlators over m msec, and analyze the n msec correlators to reduce interference. The method includes summing, by an interference mitigation processor, n msec received correlators over m msec; and analyzing, by an interference mitigation processor, the n msec correlators to reduce interference.

A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

A signal input from a microphone is A-D converted by an A-D converter, is frequency differentiated by a pre-emphasis circuit, and is input to a shift control circuit. The shift control circuit includes a limiter circuit, a phase shifter, and a harmonic suppressor. The limiter circuit performs amplitude limitation so as to limit the amplitude of the input control target signal to be equal to or less than a first threshold. The phase shifter shifts, for the control target signal having the amplitude limited, a phase of a frequency component within the predetermined frequency range. The harmonic suppressor suppresses, for the control target signal phase-shifted by the phase shifter, a frequency component equal to or greater than a second threshold, and outputs an information signal that is the control target signal having the frequency component of equal to or greater than the second threshold suppressed. The modulator performs frequency modulation on a carrier wave in accordance with the information signal. The transmitter produces a transmission signal from the frequency-modulated carrier wave, and transmits the transmission signal via an antenna.

A signal input from a microphone is A-D converted by an A-D converter, is frequency differentiated by a pre-emphasis circuit, and is input to a shift control circuit. The shift control circuit includes a limiter circuit, a phase shifter, and a harmonic suppressor. The limiter circuit performs amplitude limitation so as to limit the amplitude of the input control target signal to be equal to or less than a first threshold. The phase shifter shifts, for the control target signal having the amplitude limited, a phase of a frequency component within the predetermined frequency range. The harmonic suppressor suppresses, for the control target signal phase-shifted by the phase shifter, a frequency component equal to or greater than a second threshold, and outputs an information signal that is the control target signal having the frequency component of equal to or greater than the second threshold suppressed. The modulator performs frequency modulation on a carrier wave in accordance with the information signal. The transmitter produces a transmission signal from the frequency-modulated carrier wave, and transmits the transmission signal via an antenna.

A shift control circuit includes a first limiter circuit, a phase shifter, a first suppressor, and a reducer. The first limiter circuit limits the amplitude of a control target signal input from a microphone, having undergone A-D conversion by an A-D convener, and frequency differentiation by a pre-emphasis circuit, and having the relative intensity of harmonic components increased. The phase shifter performs, for the control target signal having undergone the amplitude limitation, phase shift on the frequency component within a first frequency range. The first suppressor suppresses, for the control target signal having undergone the phase shift, the frequency component equal to or greater than a second threshold. The reducer suppresses, for the control target signal having the suppressed frequency component, the frequency component within a second frequency range, and outputs as an information signal. A modulator performs frequency modulation on a carrier wave in accordance with the information signal, and a transmitter produces a transmission signal from the carrier wave having undergone the frequency modulation, and transmits the transmission signal via an antenna.

A shift control circuit includes a first limiter circuit, a phase shifter, a first suppressor, and a reducer. The first limiter circuit limits the amplitude of a control target signal input from a microphone, having undergone A-D conversion by an A-D convener, and frequency differentiation by a pre-emphasis circuit, and having the relative intensity of harmonic components increased. The phase shifter performs, for the control target signal having undergone the amplitude limitation, phase shift on the frequency component within a first frequency range. The first suppressor suppresses, for the control target signal having undergone the phase shift, the frequency component equal to or greater than a second threshold. The reducer suppresses, for the control target signal having the suppressed frequency component, the frequency component within a second frequency range, and outputs as an information signal. A modulator performs frequency modulation on a carrier wave in accordance with the information signal, and a transmitter produces a transmission signal from the carrier wave having undergone the frequency modulation, and transmits the transmission signal via an antenna.

A synthesizer circuit to generate a local oscillator carrier signal for a baseband signal includes a controlled oscillator comprising a phase lock loop and an oscillator configured to generate an oscillating signal. A pulling compensation circuit is configured to generate a correction signal for a present output of the phase locked loop using information on an error of the oscillating signal, information on a present sample of a baseband signal and a preceding correction signal for a preceding output of the phase locked loop.