A method for calibrating a light smart watch includes: providing an FPC soft board under a dial, a size of the FPC soft board matching a size of the dial, the FPC soft board is divided into a plurality of partitions, each partition is insulated from other partitions, and each of watch hands and each partition form a capacitor in turn when the watch hands run; detecting a capacitance change amount of each partition, determining positions of partitions where the watch hands are currently located, and determining a current time indicated by the watch hands, according to the positions of partitions where the watch hands are currently located; comparing the current time indicated by the watch hands with a current time of a mobile terminal to determine a time error; and adjusting the watch hands, according to the time error to run in sync with the time of the mobile terminal.

A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.

A method of frequency search and error correction of clock and data recovery circuit, comprising: initializing a frequency search algorithm parameter; processing a frequency error parameter UP/DN signals according to the set algorithm parameter and starting the frequency search, in which, the algorithm accordingly counts the UP/DN signals. When a phase error signal transition occurs, a transition parameter JUMP is accumulated by 1, and an accumulation parameter SUM is obtained and is further judged that whether a frequency search result is to be output. Number of repeating times of verification and threshold parameters are set, accordingly a reset DCRL value is obtained to verifies a frequency locking result and outputs the result. The present invention improves accuracy of UP/DN pulse counting, increases stability and reliability of the frequency locking, avoids a false locking in the frequency locking, and prevents an excessive locking time in the frequency locking, overcomes error judgment of the frequency search caused by a random jitter, and correctly completes the frequency search and locking, avoids failure of the CDR caused by an error frequency locking.

A method for providing a jitter signal for modulating a switching frequency of a power switch for a power converter. The method comprising receiving a drive signal representative of the switching frequency of the power switch, detecting the switching frequency from the drive signal, determining if the switching frequency is less than a first threshold frequency, and modulating a frequency of the jitter signal in response to determining if the switching frequency is less than the first threshold frequency.

A communication apparatus includes a first counter configured to synchronize with a reference time, a second counter configured to synchronize with the first counter, a generation unit configured to generate a synchronization signal each time when a value of the second counter is incremented by a predetermined number, a correction unit configured to correct the value of the second counter toward a value of the first counter, and a control unit configured to control the correction unit to cause the correction unit to calculate a difference between the value of the first counter and the value of the second counter and, in a case where the calculated difference is greater than a predetermined threshold value, the correction unit to correct the value of the second counter step by step.

A clock and data recovery circuit includes a phase detector that outputs phase characteristic data based on a digital data signal and an adjustment circuit that adjusts phase characteristic data. The clock and data recovery circuit sets an adjustment value in an adjustment circuit by calculating an adjustment value of phase characteristic data using a monitor circuit while changing a phase of a reference clock signal to be adjusted in a phase interpolation circuit based on offset data output from an offset output circuit in a training period before communication starts.

A frequency synthesizer with microcode control that allows one or more programmable circuits of a frequency synthesizer system to be programmed using a plurality of microcode instructions. A method includes, setting a frequency synthesizer system to operate in a microcode mode, programming the frequency synthesizer system for microcode execution of a plurality of microcode instructions and executing the plurality of microcode instructions at the frequency synthesizer system to control one or more behaviors of one or more programmable circuits of the frequency synthesizer system.

Systems and methods for automatically controlling one or more parameters of a digital phase-locked loop (DPLL) circuit are provided. A phase error signal generated by a phase detector of the DPLL circuit is received. A delayed version of the phase error signal is generated. A product of the phase error signal and the delayed version of the phase error signal is generated. The product is integrated, and a first output for controlling a gain of a proportional path of the DPLL circuit is generated based on the integrated product. The first output is down-sampled. A least-mean-square (LMS) filter is used to generate a second output that minimizes a value of the down-sampled output. A gain of an integral path of the DPLL is controlled based on the second output.

A clock recovery circuit a first phase-locked loop (PLL) circuit configured to perform a coarse phase fixing operation on a test data signal by using a first reference clock signal, the test data signal having a prescribed pattern, and a second PLL circuit configured to perform a fine phase fixing operation on the test data signal, subsequently to the coarse phase fixing operation. The second PLL circuit may be configured to perform the fine phase fixing operation on the test data signal by selectively using at least two selection reference clock signals among a plurality of second reference clock signals that are delayed from the first reference clock signal by a unit phase, in a training mode, having a phase difference of N times the unit phase, where N is an integer equal to or greater than 2.

A clock and data recovery circuit includes a phase detector, an adder, and an oscillator circuit. The phase detector includes a sampling circuit, a comparison circuit, and a resampling circuit. The sampling circuit includes first through fourth flip-flops for receiving a data signal and first through fourth clock signals, and generating first through fourth sampling signals. The comparison circuit includes first through fourth logic gates for receiving the first through fourth sampling signals and generating first through fourth comparison signals, respectively. The resampling circuit includes fifth through eighth flip-flops for receiving the first through fourth comparison signals and the first through fourth clock signals, and generating first through fourth control signals, respectively. The adder receives the first through fourth control signals, and generates a frequency control signal. The oscillator circuit receives the frequency control signal, generates the first through fourth clock signals.