A method is provided. The method includes estimating adjacent channel leakage ratios respectively corresponding based on a test output signal output from a power amplifier according to a test input signal corresponding to a plurality of frequencies; selecting a test delay value corresponding to a largest value among the estimated adjacent channel leakage ratios; and providing a supply voltage to the power amplifier based on an envelope signal delayed according to the selected test delay value. For each of the plurality of test delay values, a corresponding adjacent channel leakage ratio is estimated based on a ratio of a magnitude of a component included in the test output signal and a magnitude of an inter-modulated component.

Disclosed herein are transconductance circuits, as well as related methods and devices. In some embodiments, a transconductance circuit may include an amplifier having a first input coupled to a voltage input of the transconductance circuit, and a switch coupled between an output of the amplifier and a second input of the amplifier.

Circuits and operating methods thereof for correcting phase errors introduced by amplifiers employing gallium nitride (GaN) transistors are described. The phase errors are caused by trapping effects exhibited by the GaN transistors. The circuits described herein pre-distort the phase of the input signal to compensate for the phase error introduced by the amplifier. Thereby, the phase of the output signal of the amplifier has a reduced phase error. For example, the output signal may have a near zero (or zero) phase error.

The present disclosure relates to a transmitter system that includes a radio frequency (RF) power amplifier (PA) and a baseband processor. The RF PA is configured to amplify an RF input signal to an RF output signal and configured to receive an analog bias adjustment signal, which is applied to correct dynamic bias errors in the RF PA caused by amplification variations that have time constants. The baseband processor, in response to an input envelope and a feedback output envelope, is configured to generate a feedback envelope error signal. Herein, the input envelope is estimated based on a baseband input signal received by the baseband processor, and the feedback output envelope is estimated based on the RF output signal. The RF input signal and the analog bias adjustment signal fed to the RF PA are generated from the baseband input signal and the feedback envelope error signal, respectively.

Disclosed is envelope tracking circuitry having an envelope tracking integrated circuit (ETIC) coupled to a power supply to provide an envelope tracked power signal to a power amplifier (PA) with a filter equalizer configured to inject an error-correcting signal into the ETIC in response to equalizer settings. Further included is PA resistance estimator circuitry having a first peak detector circuit configured to capture within a window first peaks associated with a sense current generated by the ETIC, a second peak detector circuit configured to capture within the window second peaks associated with a scaled supply voltage corresponding to the envelope tracked power signal, comparator circuitry configured to receive the first peaks and receive the second peaks and generate an estimation of PA resistance, and an equalizer settings correction circuit configured to receive the estimation of PA resistance and update the equalizer settings in response to the estimation of PA resistance.

An analog front-end device includes an amplifier circuit, a first gain control circuit, and a tracking circuit. The amplifier circuit is configured to generate a first output signal according to a first input signal. The first gain control circuit is configured to set a first electronic component according to a first gain control signal and transmit the first input signal to a first input terminal of the amplifier circuit via the first electronic component, in which a terminal of the first electronic component is selectively coupled to the first input terminal or a first predetermined node. The tracking circuit is configured to adjust a level of the first predetermined node according to a level of the first input terminal, in order to reduce a voltage difference between the first input terminal and the first predetermined node.

Envelope tracking power amplifiers with advanced gain shaping are provided. In certain implementations, a power amplifier system includes a power amplifier that amplifies a radio frequency (RF) signal and an envelope tracker that controls a voltage level of a supply voltage of the power amplifier based on an envelope of the RF signal. The power amplifier system further includes a gain shaping circuit that generates a gain shaping current that changes with the voltage level of the supply voltage from the envelope tracker. For example, the gain shaping circuit can include an analog look-up table (LUT) mapping a particular voltage level of the supply voltage to a particular current level of gain shaping current. Additionally, the gain shaping circuit biases the power amplifier based on the gain shaping current.

A system for adapting the voltage of a drain of a power stage includes at least two transmission paths T.sub.Xa, a transmission path comprising a resistive element (1.sub.n), a phase control module (2.sub.n), and a power stage (3.sub.n) at the output of which a radiating element (E.sub.n) is arranged, comprising at least: a device (5.sub.n) for determining the value of a reflected power P.sub.r, the value of an incident power P.sub.i in a power stage, and the ratio of the powers R, an analogue device (6.sub.n) configured so as to pulse width-modulate the difference signal, a switching cell (7.sub.n) receiving a low-power PWM signal and designed to generate a power signal PWM.sub.a that is transformed, by a low-pass filter (8.sub.n), into a bias signal for biasing the power stage in accordance with a predefined bias control law.

A fast-switching average power tracking (APT) power management integrated circuit (PMIC) is provided. The fast-switching APT PMIC includes a voltage amplifier(s) and an offset capacitor(s) having a small capacitance (e.g., between 10 nF and 200 nF). The voltage amplifier(s) is configured to generate an initial APT voltage(s) based on an APT target voltage(s) and the offset capacitor(s) is configured to raise the initial APT voltage(s) by an offset voltage(s) to generate an APT voltage(s). In embodiments disclosed herein, the offset voltage(s) is modulated based on the APT target voltage(s). Given the small capacitance of the offset capacitor(s), it is possible to adapt the offset voltage(s) fast enough to thereby change the APT voltage(s) within a predetermined temporal limit (e.g., 0.5 μs). As a result, the fast-switch APT PMIC can enable a power amplifier(s) to support dynamic power control with improved linearity and efficiency.

In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.