Patent classifications
H03F1/301
TWO-TEMPERATURE TRIMMING FOR A VOLTAGE REFERENCE WITH REDUCED QUIESCENT CURRENT
In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (R.sub.DEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (R.sub.PTAT) of the differential amplifier stage, a third resistor (R1.sub.PTAT) of the scaling amplifier stage, and a fourth resistor (R2.sub.PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.
RECEIVER CONTROL CIRCUIT AND TERMINAL
Disclosed are a receiver control circuit and a terminal. The receiver control circuit includes: a smart power amplifier module, a coder-decoder, and a receiver. The smart power amplifier module is electrically connected to the receiver by a first switch module. The first switch module includes a first switch component unit that is formed by a metal oxide semiconductor field-effect transistor (MOSFET). The first switch module further includes a first follower unit, where the first follower unit is configured to keep an unchanged voltage difference between a gate electrode of the MOSFET of the first switch component unit and a drain electrode thereof, and a gate electrode voltage of the MOSFET of the first switch component unit is greater than a drain electrode voltage thereof. The coder-decoder is electrically connected to the receiver by the second switch module. The second switch module includes a second switch component unit.
BIAS CIRCUIT OF POWER AMPLIFIER, DEVICE AND EQUIPMENT
A bias circuit of a power amplifier includes a first part circuit, a second part circuit and a power supply, in which the power supply is connected with a power supply end of the first part circuit; two ends of the first part circuit are connected in parallel with two ends of the second part circuit, and after parallel connection one end of a parallel circuit is connected with a gate of the first transistor of the power amplifier in a signal amplification circuit; the first part circuit is configured to provide a first bias voltage, and the second part circuit is configured to provide a second bias voltage; the two bias voltages are superimposed to provide a stable bias voltage; and an impedance of the bias circuit is in a preset range of the impedance.
DYNAMIC COMMON-MODE ADJUSTMENT FOR POWER AMPLIFIERS
Aspects of the present disclosure relate to apparatus and methods for dynamically adjusting the common-mode input signal of a power amplifier, such as a class-D power amplifier. One example power amplifier circuit generally includes a first amplifier having a signal input and a power input; and a common-mode adjustment circuit having a first input coupled to the power input of the first amplifier, having an output coupled to the signal input of the first amplifier, and being configured to generate a common-mode signal to apply to the signal input of the first amplifier, based on a power supply voltage on the power input of the first amplifier.
LOAD DRIVE DEVICE
Achieved is a load drive device capable of suppressing local concentration of temperature at the time of absorbing a counter electromotive force of an inductive load while suppressing a size of a power transistor. The load drive device includes a first transistor connected between a first control electrode and an inductive load. Further, the load drive device includes an active clamp circuit that becomes conductive when a terminal voltage of a second control electrode between the first transistor and the inductive load exceeds a threshold. Furthermore, the load drive device includes a second transistor connected to the second control electrode and connected in parallel to the first transistor.
BANDGAP AMPLIFIER BIASING AND STARTUP SCHEME
Systems and circuits include an amplifier having an output; a switching circuit coupled to the output of the amplifier to provide a bias current to bias the amplifier; first current generating circuitry coupled to the switching circuit; and second current generating circuitry coupled to the output of the amplifier and to the switching circuit. In operation, the switching circuit provides the bias current, during a first time period, in response to a first signal generated by the first current generating circuitry, and provides the bias current, during a second time period, after the first time period, in response to a second signal generated by the second current generating circuitry.
COMPENSATION CIRCUIT OF AMPLITUDE MODULATION-PHASE MODULATION, RADIO FREQUENCY POWER AMPLIFIER AND DEVICE
An amplitude modulation-phase modulation compensation circuit includes a detection circuit, a reconfigurable current control voltage source circuit and a phase shifting circuit, in which, the detection circuit is configured to detect the power of an input signal and output a control current according to the power of the input signal when the power of the input signal is greater than a preset power threshold; the reconfigurable current control voltage source circuit is configured to generate a bias voltage according to the control current; the phase shifting circuit is configured to compensate the AM-PM distortion of the radio frequency power amplifier according to the bias voltage. In this way, by the compensation circuit, when the power of the input signal is greater than a preset power threshold, the AM-PM distortion of the radio frequency power amplifier can be compensated according to the power of the input signal.
BIAS CIRCUIT AND AMPLIFIER
A bias circuit includes a mirror current source and a current-to-voltage converter. A first terminal of the mirror current source is connected to a supply voltage terminal, a second terminal of the mirror current source is connected to a reference voltage terminal, and a third terminal of the mirror current source is connected to the current-to-voltage converter. A mirror current source is configured to acquire a supply voltage transmitted at the supply voltage terminal through the first terminal, acquire a reference voltage transmitted at the reference voltage terminal through the second terminal, and regulate the supply voltage by using the reference voltage and a preset parameter to obtain a mirror current corresponding to the supply voltage. The preset parameter is parameter information of the mirror current source. The current-to-voltage converter is configured to convert the mirror current into a voltage to provide a bias voltage based on the voltage.
Amplifier, amplification circuit and phase shifter
Amplifiers, amplification circuits, and phase shifters, for example, for flexibly adjusting an output phase to thereby meet a requirement of a constant phase on a link in a communications field, are provided. In one aspect, an amplifier includes first, second, and third MOS transistors. The first MOS transistor includes a gate separately coupled to a signal input end and a bias voltage input end, a source coupled to a power supply, and a drain separately coupled to sources of the second and third MOS transistors. A drain of the third MOS transistor is coupled to a ground, and a drain of the second MOS transistor is coupled to a signal output end. The bias voltage input end is configured to receive a bias voltage to adjust a phase difference between an input signal at the signal input end and an output signal at the signal output end.
COMPENSATION CIRCUIT AND CHIP, METHOD, APPARATUS, STORAGE MEDIUM, AND ELECTRONIC DEVICE
A compensation circuit, chip, method and device, a storage medium, and an electronic device are disclosed. The compensation circuit may include an analog module (102) including an input node (1022) and an output node (1024), wherein the input node (1022) is configured to receive an input signal and the output node (1024) is configured to output an output signal; and a linearity compensation module (104) including a plurality of transconductance units (1042), where the plurality of transconductance units (1042) are configured to acquire a first configuration signal and configure a combination of the plurality of transconductance units (1042) based on the first configuration signal to provide a compensation signal to the output node (1024), and the first configuration signal is configured to indicate a signal at any position in the analog module (102).