A voltage dividing capacitor circuit includes first capacitor through third capacitor dividers and first through fourth load capacitors. The first capacitor divider includes a first flying capacitor and a plurality of first switches connected in series between a first voltage node and a ground node, and is connected to a second voltage node. The second capacitor divider is connected to the first voltage node, the second voltage node, and a first intermediate voltage node. The third capacitor divider is connected to the second voltage node, the ground voltage node, and a second intermediate voltage node. The first through fourth load capacitors are connected in series between the first voltage node and the ground node. The second capacitor divider includes a second flying capacitor and a plurality of second switches connected in series between the first voltage node and the second voltage node.

A method is provided. The method includes estimating adjacent channel leakage ratios respectively corresponding based on a test output signal output from a power amplifier according to a test input signal corresponding to a plurality of frequencies; selecting a test delay value corresponding to a largest value among the estimated adjacent channel leakage ratios; and providing a supply voltage to the power amplifier based on an envelope signal delayed according to the selected test delay value. For each of the plurality of test delay values, a corresponding adjacent channel leakage ratio is estimated based on a ratio of a magnitude of a component included in the test output signal and a magnitude of an inter-modulated component.

A package or a chip including a linear amplifier and a power amplifier is provided, wherein the linear amplifier is configured to receive an envelope tracking signal to generate an amplified envelope tracking signal, the power amplifier is supplied by an envelope tracking supply voltage comprising a DC supply voltage and the amplified envelope tracking signal, and the power amplifier is configured to receive an input signal to generate an output signal.

Fast envelope tracking systems are provided herein. In certain embodiments, an envelope tracking system for a power amplifier includes a switching regulator and a differential error amplifier configured to operate in combination with one another to generate a power amplifier supply voltage for the power amplifier based on an envelope of a radio frequency (RF) signal amplified by the power amplifier. The envelope tracking system further includes a differential envelope amplifier configured to amplify a differential envelope signal to generate a single-ended envelope signal that changes in relation to the envelope of the RF signal. Additionally, the differential error amplifier generates an output current operable to adjust a voltage level of the power amplifier supply voltage based on comparing the single-ended envelope signal to a reference signal.

Circuits and operating methods thereof for correcting phase errors introduced by amplifiers employing gallium nitride (GaN) transistors are described. The phase errors are caused by trapping effects exhibited by the GaN transistors. The circuits described herein pre-distort the phase of the input signal to compensate for the phase error introduced by the amplifier. Thereby, the phase of the output signal of the amplifier has a reduced phase error. For example, the output signal may have a near zero (or zero) phase error.

An apparatus for providing a supply control signal for a supply unit, the supply unit being configured to provide a variable controlled power supply to the power amplifier. The apparatus includes a determination module configured to determine a deviation of a signal from at least one nominal value; and an adjustment module configured to provide the supply control signal after an adjustment based on the determined deviation.

The present disclosure relates to a transmitter system that includes a radio frequency (RF) power amplifier (PA) and a baseband processor. The RF PA is configured to amplify an RF input signal to an RF output signal and configured to receive an analog bias adjustment signal, which is applied to correct dynamic bias errors in the RF PA caused by amplification variations that have time constants. The baseband processor, in response to an input envelope and a feedback output envelope, is configured to generate a feedback envelope error signal. Herein, the input envelope is estimated based on a baseband input signal received by the baseband processor, and the feedback output envelope is estimated based on the RF output signal. The RF input signal and the analog bias adjustment signal fed to the RF PA are generated from the baseband input signal and the feedback envelope error signal, respectively.

Voltage ripple reduction in a power management circuit is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage and an envelope tracking integrated circuit (ETIC) configured to provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, an output impedance presenting at an input of the power amplifier circuit can interact with a modulated load current in the power amplifier circuit to create a voltage ripple in the modulated voltage to potentially cause an undesirable error in the RF signal. Herein, the ETIC is configured to modify the modulated voltage based on feedback of the voltage ripple in the modulated voltage. As such, it is possible to reduce the output impedance at the input of the power amplifier circuit to thereby reduce the voltage ripple in the modulated voltage.

An amplifier circuit is configured in such a way that the amplifier circuit includes: a first amplifier to amplify a signal to be amplified; an output matching circuit through which the signal amplified by the first amplifier propagates; and a second amplifier to amplify the signal which has propagated through the output matching circuit, and the output matching circuit is a lumped constant circuit including multiple lumped constant elements, and, by using the multiple lumped constant elements, transforms the impedance seen on the second amplifier side from the first amplifier when the output power of the second amplifier is lower than saturation electric power, to impedance higher than impedance seen on the second amplifier side from the first amplifier when the output power of the second amplifier is equal to the saturation electric power.

A maximum current detection circuit with multiple input current ports and a maximum current port generates, on the maximum current port, a maximum current corresponding to the largest input current on one of the input current ports. The maximum current detection circuit includes multiple current mirror circuits, each controlled by one of the input currents. Each of the current mirror circuits includes outputs, each coupled to a respective one of the input current ports and the maximum current port. The current mirror circuit controlled by the largest input current becomes the dominant source for the input currents on each of the input current ports and also drives the maximum current on the maximum current port. The input currents may be single-ended or differential signals. The input currents may be respectively delayed signals of a windowing circuit in an envelope tracking circuit controlling a power amplifier of a wireless device.