Patent classifications
H03F2200/108
Body tie optimization for stacked transistor amplifier
A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.
Tunable vector recombination amplifier
A tunable vector recombination amplifier comprises an input, an output, first and second amplifier circuit paths each including a respective phase shifter to receive a respective input signal from the input and to apply a respective phase shift to produce a respective phase-shifted signal, a respective interstage impedance matching network, and a respective amplifier connected between the respective phase shifter and interstage impedance matching network to receive and amplify the respective phase-shifted signal to produce a respective amplified signal, first and second controllable DC voltage sources each coupled to a respective amplifier and configured to provide a respective supply voltage to the respective amplifier, values of the supply voltages being independently controllable, and an output amplifier stage to receive, amplify, and vectorially combine the amplified signals to produce a combined signal having a specified phase determined by the phase shifts and supply-voltage values and a specified amplitude at the output.
Scalable periphery tunable matching power amplifier
A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.
GROUP III NITRIDE BASED DEPLETION MODE DIFFERENTIAL AMPLIFIERS AND RELATED RF TRANSISTOR AMPLIFIER CIRCUITS
An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.
POWER AMPLIFICATION CIRCUIT
A power amplification circuit that includes: a capacitor element in which a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer are sequentially stacked, the capacitor element including a first capacitor in which the first metal layer serves as one electrode thereof and the second metal layer serves as another electrode thereof, and a second capacitor in which the second metal layer serves as one electrode thereof and the third metal layer serves as another electrode thereof; and a transistor that amplifies a radio-frequency signal. The radio-frequency signal is supplied to the one electrode of the first capacitor. The other electrode of the first capacitor and the one electrode of the second capacitor are connected to a base of the transistor, and the other electrode of the second capacitor is connected to the emitter of the transistor.
ELECTRIC POWER CONVERTER AND POWER AMPLIFIER
An electric power converter includes a first capacitor being located between an input terminal and an output terminal, and that connects a first terminal being located between the input terminal and a ground, a reactor that connects through electric contact between the first terminal and the output terminal, a switching element that connects through electric contact between the input terminal and the output terminal, and a control unit that executes a first PWM control process controlling a pulse width of the PWM waveform by on and off of the switching device according to the fluctuation of the output voltage, and that executes a second PWM control process widening a pulse width of the PWM and a duty cycle of a PWM than those of the previous cycle when a pulse width becomes a lower limit.
FULLY INTEGRATED LOW-NOISE AMPLIFIER
A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.
SEMICONDUCTOR DEVICE AND TRANSMITTER
An amplifier has a plurality of gate finger electrodes, two gate connection electrodes, a plurality of source electrodes and a plurality of drain electrodes, and a plurality of drain connection elements. The plurality of gate finger electrodes are arranged pectinate on the surface of the active region of the semiconductor substrate. The two gate connection electrodes connect in common each of both ends of the plurality of gate finger electrodes. The plurality of source electrodes and the plurality of drain electrodes are arranged alternately on the surface of the semiconductor substrate between the plurality of gate finger electrodes. The plurality of drain connection elements connects in sequence the plurality of drain electrodes. The ratio of the inductance value of each drain connection element to the parasitic capacitance of the drain-source electrodes between the corresponding drain electrode and the source electrode is constant.
CIRCUITS, DEVICES AND METHODS FOR REDUCING CO-CHANNEL INTERFERENCE
Circuits, devices and methods are disclosed, including radio-frequency circuitry comprising a polar modulator configured to invert a sampled transmitted signal into an inverted sampled transmitted signal, a signal combiner configured to combine the inverted sampled transmitted signal with a received signal and a control logic circuit coupled to the polar modulator, the control logic circuit configured to adjust one or more tuning parameters of the polar modulator for inverting the sampled transmitted signal.
RADIO-FREQUENCY MODULE
A semiconductor device including a radio-frequency amplifier circuit and a band selection switch is mounted on or in a module substrate. An output matching circuit coupled between the radio-frequency amplifier circuit and the band selection switch is on or in the module substrate. The semiconductor device includes a first member at which the band selection switch having a semiconductor element made of an elemental semiconductor is formed and a second member joined to the first member in surface contact therewith. The radio-frequency amplifier circuit including a semiconductor element made of a compound semiconductor is formed at the second member. Conductive protrusions are raised from first and second members. The semiconductor device is mounted on or in the module substrate with the conductive protrusions interposed therebetween, and in plan view, is in close proximity to the output matching circuit or overlaps a passive element constituting the output matching circuit.