A read-out circuit includes an operational amplifier configured to receive an input voltage through a positive input terminal; a feedback capacitor connected between an output terminal of the operational amplifier and a negative input terminal of the operational amplifier; a sensor charging and discharging circuit configured to charge or discharge a sensor during a first time; a switching circuit connecting the sensor and the operational amplifier during a second time after the sensor is charged or discharged; and a duty control circuit configured to determine a duty ratio of the first time and the second time according to a capacitance of the sensor.

A read-out circuit includes an operational amplifier configured to receive input voltage via a positive input terminal; a feedback capacitor connected between an output terminal of the operational amplifier and a negative input terminal of the operational amplifier; a sensor charging/discharging circuit configured to charge or to discharge a sensor capacitor included in a sensor during a first time; and a switching circuit configured to connect the sensor capacitor and the operational amplifier during a second time after the sensor capacitor is charged or discharged.

An acoustic feature extraction (AFE) circuit includes a plurality of band-pass filters (BPFs) adaptable to a plurality of channels with different band-pass frequency ranges respectively for switchably receiving an amplified signal, thereby generating corresponding filtered signals, the plurality of BPFs including an operational amplifier that is shared among the plurality of channels; and a rectifier switchably coupled to receive the filtered signals, thereby generating a rectified signal. The amplified signal is time-division demultiplexed onto the BPFs in different phases, and the filtered signals are time-division multiplexed onto the rectifier in different phases.

A line receiver comprising a switched capacitor circuit and a buffer is described. The buffer may be configured to receive, through the switched capacitor circuit, an analog signal. In response, the buffer may provide an output signal to a load, such as an analog-to-digital converter. The switched capacitor circuit may be controlled by a control circuitry, and may charge at least one capacitive element to a desired reference voltage. The reference voltage may be selected so as to bias the buffer with a desired DC current, and consequently, to provide a desired degree if linearity. The line receiver may further comprise a bias circuit configured to generate the reference voltage needed to bias the buffer with the desired DC current.

An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

An amplifier is configured to amplify an RF signal as between an input terminal and an output terminal across a wideband frequency range. A first LC network is connected to the input terminal and has first and second reactive components. A first switching device is connected between the first and second reactive components and couples both the first and second reactive components to the input terminal in an ON state, and disconnects the second reactive component from the input terminal in an OFF state. A second LC network is connected to the output terminal and has third and fourth reactive components. A second switching device is connected between the third and fourth reactive components and couples both the third and fourth reactive components to the output terminal in an ON state and disconnects the fourth reactive component from the output terminal in in an OFF state.

A power amplifier, a power amplifier system, and an operating method thereof are provided. The power amplifier system may include a power amplifier, a power amplifier controller, and a voltage generator. The power amplifier may include a plurality of power transistor cells each of which receives an RF signal through a control terminal thereof to amplify the RF signal. The power amplifier controller may control turn-on and turn-off operations of at least one power transistor cell among the plurality of power transistor cells based on a power mode. The voltage generator may generate a power supply voltage supplied to first terminals of the power transistor cells and may change the power supply voltage depending on the power mode.

The invention relates to a class AB amplifier for receiving an input current and generating an amplified output current and having first and second output transistors connected to provide the output current, wherein if the input current is less than a threshold the first output transistor is enabled and the second output transistor is disabled, and if the input current exceeds a threshold the second output transistor is enabled.

Amplifiers with wide input range and low input capacitance are provided. In certain embodiments, an amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and/or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to decouple the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to decouple the input terminals from the p-type input transistors when unused.

The present disclosure relates to a device comprising two error amplifier stages having their first inputs interconnected, their second inputs interconnected and their outputs coupled to an output of the device, each stage comprising an operational amplifier; a circuit for calibrating the amplifier; a switch coupling an input of the amplifier to the first input; a switch coupling another input of the amplifier to the second input; a switch coupling an output of the amplifier to the stage output; a switch having on state which short-circuits the inputs of the amplifier; and a switch coupling the output of the amplifier to the calibration circuit.