A Doherty amplifier is configured in such a way that a phase adjustment circuit adjusts either the phase of a return signal going to a first auxiliary amplification element as a result of passage of a first signal amplified by a second main amplification element through a second auxiliary amplification element as the return signal, or the phase of the return signal going to the second auxiliary amplification element as a result of reflection of the return signal by the first auxiliary amplification element, at a time of a backoff operation of the second auxiliary amplification element, in such a way that the sum of the phase of the return signal going to the first auxiliary amplification element and the phase of the return signal going to the second auxiliary amplification element is not equal to 0 degrees in the operating frequency band of the first signal.

Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.

A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

An RF amplifier comprises a first ‘transconductance’ transistor (N.sub.CS) arranged to receive an RF input voltage (RFIN) at its gate terminal. A second ‘cascode’ transistor (N.sub.CG) has its source terminal connected to the drain terminal of the first transistor (N.sub.CS) at a node (MID). A feedback circuit portion is configured to measure a node voltage at the node (MID), to determine an average of the node voltage, to compare said average node voltage to a predetermined reference voltage (V.sub.BCG), and to generate a control voltage (CGGATE) dependent on the difference between the average node voltage and the predetermined reference voltage (V.sub.BCG). The feedback circuit portion applies the control voltage (CGGATE) to the gate terminal of the second transistor (N.sub.CG).

A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.

A testing system includes: a signal generator arranged to generate a testing signal; a dividing circuit coupled to the signal generator for providing a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit for being tested by generating a plurality of output signals for a predetermined testing time according to the plurality of input signals respectively.

A power amplifier apparatus includes a semiconductor substrate, a plurality of first transistors on the semiconductor substrate, a plurality of second transistors, at least one collector terminal electrically connected to collectors of the plurality of first transistors, a first inductor having a first end electrically connected to the collector terminal and a second end electrically connected to a power supply potential, at least one emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction, a second inductor having a first end electrically connected to the emitter terminal and a second end electrically connected to a reference potential, and at least one capacitor having a first end electrically connected to the collectors of the plurality of first transistors and a second end electrically connected to the emitters of the plurality of second transistors.

A receiver front end (300) having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch (260) is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

A Doherty power amplifier circuit having a main power amplification device, an auxiliary power amplification device arranged in parallel with the main power amplification device, and a load modulation circuit comprising a harmonic injection circuit connected with respective outputs of the main power amplification device and the auxiliary power amplification device. The harmonic injection circuit is arranged to transfer harmonic components generated at the main power amplification device to the auxiliary power amplification device and harmonic components generated at the auxiliary power amplification device to the main power amplification device, when both the main and auxiliary power amplification devices are operating, for modulating the respective outputs of the main power amplification device and the auxiliary power amplification device.