A transceiver is configured for a calibration mode of operation in which an impedance of a transmit chain is tuned responsive to a power measurement of a mixed RF calibration signal to form a tuned transmit chain. A direct conversion mixes an RF calibration signal with a DC offset signal to form the mixed calibration signal. During a normal mode of operation, a heterodyne mixer mixes an LO signal with an IF signal to produce an RF signal that is amplified through the tuned transmit chain.

A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration.

A radio frequency module includes: a module board that includes a first principal surface and a second principal surface on opposite sides of the module board; a power amplifier; and a first circuit component. The power amplifier includes: a first amplifying circuit element; a second amplifying circuit element; and an output transformer that includes a primary coil and a secondary coil. An end of the primary coil is connected to an output terminal of the first amplifying circuit element. Another end of the primary coil is connected to an output terminal of the second amplifying circuit element. An end of the secondary coil is connected to an output terminal of the power amplifier. The first amplifying circuit element and the second amplifying circuit element are disposed on the first principal surface. The first circuit component is disposed on the second principal surface.

When a current-to-voltage converter is used at low temperatures, the frequency band of measurable small currents is limited. Stray capacitance of a coaxial cable that takes out an output voltage of the current-to-voltage converter from inside to outside a cooling device narrows the operating frequency band of the current-to-voltage converter. The current-to-voltage converter of the present disclosure uses elements exclusively optimized for low-temperature operation (e.g., HEMTs) as electronic elements for current-to-voltage conversion. This configuration realizes current-to-voltage conversion characteristics with significantly more excellent sensitivity than that of the conventional technique even when the current-to-voltage converter is operated at a low temperature of 150 K or less or in cryogenic temperature conditions close to absolute zero. Further, a source follower circuit is added to an output stage of the current-to-voltage conversion circuit to isolate the effect of stray capacitance added to the output side of the current-to-voltage conversion circuit and achieve a wider bandwidth.

A transceiver is configured for a calibration mode of operation in which an impedance of a transmit chain is tuned responsive to a power measurement of a mixed RF calibration signal to form a tuned transmit chain. A direct conversion mixes an RF calibration signal with a DC offset signal to form the mixed calibration signal. During a normal mode of operation, a heterodyne mixer mixes an LO signal with an IF signal to produce an RF signal that is amplified through the tuned transmit chain.

Doherty power amplifiers and devices are described with a low voltage driver stage in a carrier-path and a high voltage driver stage in a peaking-path. In an embodiment a Doherty power amplifier has a carrier-path driver stage transistor configured to operate using a first bias voltage at the driver stage output, and a final stage transistor configured to operate using a second bias voltage at the final stage output. A peaking-path driver stage transistor is configured to operate using a third bias voltage at the driver stage output, and a final stage transistor electrically coupled to the driver stage output of the peaking-path driver stage transistor is configured to operate using a fourth bias voltage at the final stage output, wherein the third bias voltage is at least twice as large as the first bias voltage.

An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.

Gain is suppressed. In a power amplification circuit, a first transistor has a first input terminal, a first output terminal, and a first ground terminal. A second transistor has a second input terminal, a second output terminal, and a second ground terminal. The second input terminal is connected to the first input terminal. The second output terminal is connected to the first output terminal. A first bias circuit is connected to the first input terminal. A second bias circuit is connected to the second input terminal. A first resistor is connected between the first ground terminal and the ground. A second resistor is connected between the second ground terminal and the ground. The second resistor has a resistance value greater than that of the first resistor.

A higher-speed operation of a power amplifier circuit is achieved. A power amplifier circuit includes multi-stage amplifier units, an ET terminal, and an APT terminal. The multi-stage amplifier units include a final-stage amplifier unit. The final-stage amplifier unit includes a first amplifier element and a second amplifier element that are connected in parallel with each other. The first amplifier element is connected to the ET terminal. The second amplifier element is connected to the APT terminal.

Example embodiments relate to hybrid Doherty power amplifier modules. One embodiment includes a printed circuit board having an input RF terminal and an output RF terminal, and on which printed circuit board a primary Doherty amplifier is integrated. The primary Doherty amplifier includes a primary Doherty splitter arranged on the printed circuit board and configured for splitting an input RF signal received at the input RF terminal into a plurality of RF signal components. The primary Doherty amplifier also includes a plurality of amplifying paths, each amplifying path being partially integrated on a semiconductor die of a first kind mounted on the printed circuit board and partially integrated on a semiconductor die of a second kind mounted on the printed circuit board. Further, the primary Doherty amplifier includes a primary Doherty combiner arranged on the printed circuit board.